Semiconductor package with front side and back side redistribution structures and fabricating method thereof

ABSTRACT

A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

The present application is a continuation of U.S. patent applicationSer. No. 16/260,674, filed Jan. 29, 2019, and titled “SEMICONDUCTORPACKAGE AND FABRICATING METHOD THEREOF,” expected to issue as U.S. Pat.No. 10,943,858; which is a continuation of U.S. patent application Ser.No. 15/854,095, filed Dec. 26, 2017, and titled “SEMICONDUCTOR PACKAGEAND FABRICATING METHOD THEREOF,” now U.S. Pat. No. 10,192,816; which isa CONTINUATION of U.S. patent application Ser. No. 15/400,041, filedJan. 6, 2017, and titled “SEMICONDUCTOR PACKAGE AND FABRICATING METHODTHEREOF,” now U.S. Pat. No. 9,852,976; which is a CONTINUATION of U.S.patent application Ser. No. 14/823,689, filed Aug. 11, 2015, and titled“SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” now U.S. Pat.No. 9,543,242; the contents of each of which are hereby incorporatedherein by reference in their entirety.

This application is related to U.S. patent application Ser. No.13/753,120, filed Jan. 29, 2013, and titled “SEMICONDUCTOR DEVICE ANDMETHOD OF MANUFACTURING SEMICONDUCTOR DEVICE”; U.S. patent applicationSer. No. 13/863,457, filed on Apr. 16, 2013, and titled “SEMICONDUCTORDEVICE AND MANUFACTURING METHOD THEREOF”; U.S. patent application Ser.No. 14/083,779, filed on Nov. 19, 2013, and titled “SEMICONDUCTOR DEVICEWITH THROUGH-SILICON VIA-LESS DEEP WELLS”; U.S. patent application Ser.No. 14/218,265, filed Mar. 18, 2014, and titled “SEMICONDUCTOR DEVICEAND MANUFACTURING METHOD THEREOF”; U.S. patent application Ser. No.14/313,724, filed Jun. 24, 2014, and titled “SEMICONDUCTOR DEVICE ANDMANUFACTURING METHOD THEREOF”; U.S. patent application Ser. No.14/444,450, Jul. 28, 2014, and titled “SEMICONDUCTOR DEVICE WITH THINREDISTRIBUTION LAYERS”; U.S. patent application Ser. No. 14/524,443,filed Oct. 27, 2014, and titled “SEMICONDUCTOR DEVICE WITH REDUCEDTHICKNESS”; U.S. patent application Ser. No. 14/532,532, filed Nov. 4,2014, and titled “INTERPOSER, MANUFACTURING METHOD THEREOF,SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD FOR FABRICATING THESEMICONDUCTOR PACKAGE”; U.S. patent application Ser. No. 14/546,484,filed Nov. 18, 2014, and titled “SEMICONDUCTOR DEVICE WITH REDUCEDWARPAGE”; and U.S. patent application Ser. No. 14/671,095, filed Mar.27, 2015, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHODTHEREOF;” the contents of each of which are hereby incorporated hereinby reference in their entirety.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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SEQUENCE LISTING

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MICROFICHE/COPYRIGHT REFERENCE

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BACKGROUND

Present semiconductor packages and methods for forming semiconductorpackages are inadequate, for example resulting in excess cost, decreasedreliability, or package sizes that are too large. Further limitationsand disadvantages of conventional and traditional approaches will becomeapparent to one of skill in the art, through comparison of suchapproaches with the present disclosure as set forth in the remainder ofthe present application with reference to the drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the present disclosure, and are incorporated in andconstitute a part of this specification. The drawings illustrateexamples of the present disclosure and, together with the description,serve to explain various principles of the present disclosure. In thedrawings:

FIGS. 1A-1J show cross-sectional views illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIG. 2 is a flow diagram of an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIGS. 3A-3B show cross-sectional views illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIGS. 4A-4D show cross-sectional views illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIGS. 5A-5F show cross-sectional views illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIGS. 6A-6D show cross-sectional views illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIGS. 7A-7L show cross-sectional views illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIG. 8 is a flow diagram of an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIG. 9 shows a cross-sectional view illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIGS. 10A-10B show cross-sectional views illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIGS. 11A-11D show cross-sectional views illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIGS. 12A-12B show cross-sectional views illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIG. 13 shows a cross-sectional view illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIG. 14 shows a cross-sectional view illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIG. 15 shows a cross-sectional view illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

FIG. 16 shows a cross-sectional view illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.

SUMMARY

Various aspects of this disclosure provide a semiconductor devicestructure and a method for making a semiconductor device. Asnon-limiting examples, various aspects of this disclosure providevarious semiconductor package structures, and methods for makingthereof, that comprise a thin fine-pitch redistribution structure.

DETAILED DESCRIPTION OF VARIOUS ASPECTS OF THE DISCLOSURE

The following discussion presents various aspects of the presentdisclosure by providing examples thereof. Such examples arenon-limiting, and thus the scope of various aspects of the presentdisclosure should not necessarily be limited by any particularcharacteristics of the provided examples. In the following discussion,the phrases “for example,” “e.g.,” and “exemplary” are non-limiting andare generally synonymous with “by way of example and not limitation,”“for example and not limitation,” and the like.

As utilized herein, “and/or” means any one or more of the items in thelist joined by “and/or”. As an example, “x and/or y” means any elementof the three-element set {(x), (y), (x, y)}. In other words, “x and/ory” means “one or both of x and y.” As another example, “x, y, and/or z”means any element of the seven-element set {(x), (y), (z), (x, y), (x,z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one ormore of x, y, and z.”

The terminology used herein is for the purpose of describing particularexamples only and is not intended to be limiting of the disclosure. Asused herein, the singular forms are intended to include the plural formsas well, unless the context clearly indicates otherwise. It will befurther understood that the terms “comprises,” “includes,” “comprising,”“including,” “has,” “have,” “having,” and the like when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another element. Thus, for example, a first element, afirst component or a first section discussed below could be termed asecond element, a second component or a second section without departingfrom the teachings of the present disclosure. Similarly, various spatialterms, such as “upper,” “lower,” “side,” and the like, may be used indistinguishing one element from another element in a relative manner. Itshould be understood, however, that components may be oriented indifferent manners, for example a semiconductor device may be turnedsideways so that its “top” surface is facing horizontally and its “side”surface is facing vertically, without departing from the teachings ofthe present disclosure.

Various aspects of the present disclosure provide a semiconductor deviceor package and a fabricating (or manufacturing) method thereof, whichcan decrease the cost, increase the reliability, and/or increase themanufacturability of the semiconductor device.

The above and other aspects of the present disclosure will be describedin or be apparent from the following description of various exampleimplementations. Various aspects of the present disclosure will now bepresented with reference to accompanying drawings, such that thoseskilled in the art may readily practice the various aspects.

FIGS. 1A-1J show cross-sectional views illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.The structures shown in 1A-1J may share any or all characteristics withanalogous structures shown in FIGS. 3A-3B, 4A-4D, 5A-5F, 6A-6D, 7A-7L,9, 10A-10B, 11A-11D, 12A-12B, 13, 14, 15, and 16 . FIG. 2 is a flowdiagram of an example method 200 of making a semiconductor package, inaccordance with various aspects of the present disclosure. FIGS. 1A-1Kmay, for example, illustrate an example semiconductor package at varioussteps (or blocks) of the method 200 of FIG. 2 . FIGS. 1A-1K and FIG. 2will now be discussed together. It should be noted that the order of theexample blocks of the method 200 may vary without departing from thescope of this disclosure.

The example method 200 may, at block 205, comprise preparing a logicwafer for processing (e.g., for packaging). Block 205 may comprisepreparing a logic wafer for processing in any of a variety of manners,non-limiting manner of which are presented herein.

For example, block 205 may comprise receiving a logic wafer, for examplefrom supplier shipping, from an upstream process at a manufacturingsite, etc. The logic wafer may, for example, comprise a semiconductorwafer that comprises a plurality of active semiconductor die. Thesemiconductor die may, for example, comprise a processor die, memorydie, programmable logic die, application specific integrated circuitdie, general logic die, etc.

Block 205 may, for example, comprise forming conductive interconnectionstructures on the logic wafer. Such conductive interconnectionstructures may, for example, comprise conductive pads, lands, bumps orballs, conductive pillars, etc. The forming may, for example, compriseattaching preformed interconnection structures to the logic wafer,plating the interconnection structures on the logic wafer, etc.

In an example implementation, the conductive structures may compriseconductive pillars comprising copper and/or nickel, and may comprise asolder cap (e.g., comprising tin and/or silver). For example, conductivestructures comprising conductive pillars may comprise: (a) an under bumpmetallization (“UBM”) structure that includes (i) a layer oftitanium-tungsten (TiW) formed by sputtering (which may be referred toas a “seed layer”), and (ii) a layer of copper (Cu) on thetitanium-tungsten layer formed by sputtering, (b) a copper pillar formedon the UBM by electroplating, and (c) a layer of solder formed on thecopper pillar or a layer of nickel formed on the copper pillar with alayer of solder formed on the nickel layer.

Also, in an example implementation, the conductive structures maycomprise a lead and/or lead-free wafer bump. For example, lead-freewafer bumps (or interconnect structures) may be formed, at least inpart, by: (a) forming an under bump metallization (UBM) structure by (i)forming a layer of titanium (Ti) or titanium-tungsten (TiW) bysputtering, (ii) forming a layer of copper (Cu) on the titanium ortitanium-tungsten layer by sputtering, (iii) and forming a layer ofnickel (Ni) on the copper layer by electroplating; and (b) forming alead free solder material on the nickel layer of the UBM structure byelectroplating, wherein the lead free solder material has a compositionby weight of 1% to 4% silver (Ag) and the remainder of the compositionby weight is tin (Sn).

Block 205 may, for example, comprise performing partial or full thinningof the logic wafer (e.g., grinding, etching, etc.). Block 205 may also,for example, comprise dicing the logic wafer into separate die or diesets for later attachment. Block 205 may also comprise receiving thelogic wafer from an adjacent or upstream manufacturing station at amanufacturing facility, from another geographical location, etc. Thelogic wafer may, for example, be received already prepared or additionalpreparation steps may be performed.

In general, block 205 may comprise preparing a logic wafer forprocessing (e.g., for packaging). Accordingly, the scope of thisdisclosure should not be limited by characteristics of particular typesof logic wafer and/or die processing.

The example method 200 may, at block 210, comprise preparing a carrier,substrate, or wafer. The prepared (or received) wafer may be referred toas a redistribution structure wafer or RD wafer. Block 210 may comprisepreparing an RD wafer for processing in any of a variety of manners,non-limiting example of which are presented herein.

The RD wafer may, for example, comprise an interposer wafer, wafer ofpackage substrates, etc. The RD wafer may, for example, comprise aredistribution structure formed (e.g., on a die-by-die basis) on asemiconductor (e.g., silicon) wafer. The RD wafer might, for example,comprise only electrical pathways and not electronic devices (e.g.,semiconductor devices). The RD wafer might also, for example, comprisepassive electronic devices but not active semiconductor devices. Forexample, the RD wafer may comprise one or more conductive layers ortraces formed on (e.g., directly or indirectly on) or coupled to asubstrate or carrier. Examples of the carrier or substrate may include asemiconductor (e.g., silicon) wafer or a glass substrate. Examples ofprocesses used to form conductive layers (e.g., copper, aluminum,tungsten, etc.) on a semiconductor wafer include utilizing semiconductorwafer fabrication processes, which may also be referred to herein asback end of line (BEOL) processes. In an example implementation, theconductive layers may be deposited on or over a substrate using aputtering and/or electroplating process. The conductive layers may bereferred to as redistribution layers. The redistribution layers may beused to route an electrical signal between two or more electricalconnections and/or to route an electrical connection to a wider ornarrower pitch.

In an example implementation, various portions of the redistributionstructure (e.g., interconnection structures (e.g., lands, traces, etc.)that may be attached to electronic devices) may be formed having asub-micron pitch (or center-to-center spacing) and/or less than a 2micron pitch. In various other implementations, a 2-5 micron pitch maybe utilized.

In an example implementation, a silicon wafer on which theredistribution structure is formed may comprise silicon that is a lowergrade than can be adequately utilized to form the semiconductor dieultimately attached to the redistribution structure. In another exampleimplementation, the silicon wafer may be a reclaimed silicon wafer froma failed semiconductor device wafer fabrication. In a further exampleimplementation, the silicon wafer may comprise a silicon layer that isthinner than can be adequately utilized to form the semiconductor dieultimately attached to the redistribution structure. Block 210 may alsocomprise receiving the RD wafer from an adjacent or upstreammanufacturing station at a manufacturing facility, from anothergeographical location, etc. The RD wafer may, for example, be receivedalready prepared or additional preparation steps may be performed.

FIG. 1A provides an example illustration of various aspects of block210. Referring to FIG. 1A, the RD wafer 100A may, for example, comprisea support layer 105 (e.g., a silicon or other semiconductor layer, aglass layer, etc.). A redistribution (RD) structure 110 may be formed onthe support layer 105. The RD structure 110 may, for example, comprise abase dielectric layer 111, a first dielectric layer 113, firstconductive traces 112, a second dielectric layer 116, second conductivetraces 115, and interconnection structures 117.

The base dielectric layer 111 may, for example, be on the support layer105. The base dielectric layer 111 may, for example, comprise an oxidelayer, a nitride layer, etc. The base dielectric layer 111 may, forexample, be formed to specification and/or may be native. Dielectriclayer 111 may be referred to as a passivation layer. Dielectric layer111 may be or comprise, for example, a silicon dioxide layer formedusing a low pressure chemical vapor deposition (LPCVD) process.

The RD wafer 100A may also, for example, comprise first conductivetraces 112 and a first dielectric layer 113. The first conductive traces112 may, for example, comprise deposited conductive metal (e.g., copper,aluminum, tungsten, etc.). Conductive traces 112 may be formed bysputtering and/or electro-plating. The conductive traces 112 may, forexample, be formed at a sub-micron or sub-two-micron pitch (orcenter-to-center spacing). The first dielectric layer 113 may, forexample, comprise an inorganic dielectric material (e.g., silicon oxide,silicon nitride, etc.). Note that in various implementations, thedielectric layer 113 may be formed prior to the first conductive traces112, for example formed with apertures which are then filled with thefirst conductive traces 112 or a portion thereof. In an exampleimplementation, for example comprising copper conductive traces, a dualdamascene process may be utilized to deposit the traces.

In an alternative assembly, the first dielectric layer 113 may comprisean organic dielectric material. For example, the first dielectric layer113 may comprise bismaleimidetriazine (BT), phenolic resin, polyimide(PI), benzo cyclo butene (BCB), poly benz oxazole (PBO), epoxy andequivalents thereof and compounds thereof, but aspects of the presentdisclosure are not limited thereto. The organic dielectric material maybe formed in any of a variety of manners, for example chemical vapordeposition (CVD). In such an alternative assembly, the first conductivetraces 112 may, for example, be at a 2-5 micron pitch (orcenter-to-center spacing).

The RD wafer 100A may also, for example, comprise second conductivetraces 115 and a second dielectric layer 116. The second conductivetraces 115 may, for example, comprise deposited conductive metal (e.g.,copper, etc.). The second conductive traces 115 may, for example, beconnected to respective first conductive traces 112 through respectiveconductive vias 114 (e.g., in the first dielectric layer 113). Thesecond dielectric layer 116 may, for example, comprise an inorganicdielectric material (e.g., silicon oxide, silicon nitride, etc.). In analternative assembly, the second dielectric layer 116 may comprise anorganic dielectric material. For example, the second dielectric layer116 may comprise bismaleimidetriazine (BT), phenolic resin, polyimide(PI), benzo cyclo butene (BCB), poly benz oxazole (PBO), epoxy andequivalents thereof and compounds thereof, but aspects of the presentdisclosure are not limited thereto. The second dielectric layer 116 may,for example, be formed using a CVD process, but the scope of thisdisclosure is not limited thereto.

Though two sets of dielectric layers and conductive traces areillustrated in FIG. 1A, it should be understood that the RD structure110 of the RD wafer 100A may comprise any number of such layers andtraces. For example, the RD structure 110 might comprise only onedielectric layer and/or set of conductive traces, three sets ofdielectric layers and/or conductive traces, etc.

As with the logic wafer prep at block 205, block 210 may compriseforming interconnection structures (e.g., conductive bumps, conductiveballs, conductive pillars, conductive lands or pads, etc.) on a surfaceof the RD structure 110. Examples of such interconnection structures 117are shown in FIG. 1A, in which the RD structure 110 comprisesinterconnection structures 117, which are shown formed on the front (ortop) side of the RD structure 110 and electrically connected torespective second conductive traces 115 through conductive vias in thesecond dielectric layer 116. Such interconnection structures 117 may,for example, be utilized to couple the RD structure 110 to variouselectronic components (e.g., active semiconductor components or die,passive components, etc.).

The interconnection structures 117 may, for example, comprise any of avariety of conductive materials (e.g., any one of or a combination ofcopper, nickel, gold, etc.). The interconnection structures 117 mayalso, for example, comprise solder.

In general, block 210 may comprise preparing a redistribution structurewafer (RD wafer). Accordingly, the scope of this disclosure should notbe limited by characteristics of any particular manner of performingsuch preparing.

The example method 200 may, at block 215, comprise forminginterconnection structures (e.g., through mold via (TMV) interconnectionstructures) on the RD wafer. Block 215 may comprise forming suchinterconnection structures in any of a variety of manners.

The interconnection structures may comprise any of a variety ofcharacteristics. For example, the interconnection structures maycomprise solder balls or bumps, multi-ball solder columns, elongatedsolder balls, metal (e.g., copper) core balls with a layer of solderover a metal core, plated pillar structures (e.g., copper pillars,etc.), wire structures (e.g., wire bonding wires), etc.

The interconnection structures may comprise any of a variety ofdimensions. For example, the interconnection structures may extend fromthe RD wafer to a height less than the heights of the electroniccomponents coupled to the RD wafer (e.g., at block 220). Also forexample, the interconnection structures may extend from the RD wafer toa height greater than or equal to the heights of the electroniccomponents coupled to the RD wafer. The significance of such relativeheights will become apparent in the discussion herein (e.g., in thediscussions of mold thinning, package stacking, top substrate attaching,top redistribution structure formation, etc.). The interconnectionstructures may also, for example, be formed at various pitches (orcenter-to-center spacing). For example, the interconnection structures(e.g., conductive posts or pillars) may be plated and/or bonded at a150-250 micron pitch or less. Also for example, the interconnectionstructures (e.g., elongated and/or metal-filled solder structures) maybe attached at a 250-350 micron pitch or less. Additionally for example,the interconnection structures (e.g., solder balls) may be attached at a350-450 micron pitch or less.

Block 215 may comprise attaching the interconnection structures in anyof a variety of manners. For example, block 215 may comprisereflow-attaching the interconnection structures on the RD wafer, platingthe interconnection structures on the RD wafer, wire-bonding theinterconnection structures on the RD wafer, attaching preformedinterconnection structures to the RD wafer with conductive epoxy, etc.

FIG. 1B provides an example illustration of various aspects of block215, for example interconnection structure formation aspects. In theexample assembly 100, the interconnection structures 121 (e.g., solderballs) are attached (e.g., reflow attached, attached using a solder balldrop process, etc.) to the RD structure 110 of the RD wafer 100A.

Though two rows of interconnection structures 121 are shown, variousimplementations may comprise a single row, three rows, or any number ofrows. As will be discussed herein, various example implementations mighthave none of such interconnection structures 121 and thus block 215might be included in example method 200.

Note that although in the example method 200, the block 215 is performedbefore the wafer molding operation at block 230, the interconnectionstructures may be formed after the wafer molding operation instead(e.g., forming via apertures in the mold material and then filling suchapertures with conductive material). Also note that block 215 may beperformed after the block 220 die attachment operation as shown in FIG.2 , for example instead of before die attachment.

In general, block 215 may comprise forming interconnection structures onthe RD wafer. Accordingly, the scope of this disclosure should not belimited by characteristics of particular types of interconnectionstructures or by characteristics of any particular manner of formingsuch interconnection structures.

The example method 200 may, at block 220, comprise attaching one or moresemiconductor die to the RD structure (e.g., of the RD wafer). Block 220may comprise attaching the die to the RD structure in any of a varietyof manners, non-limiting examples of which are provided herein.

The semiconductor die may comprise characteristics of any of a varietyof types of semiconductor die. For example, the semiconductor die maycomprise a processor die, a memory die, an application specificintegrated circuit die, general logic die, active semiconductorcomponents, etc.). Note that passive components may also be attached atblock 220.

Block 220 may comprise attaching the semiconductor die (e.g., asprepared at block 205) in any of a variety of manners. For example,block 220 may comprise attaching the semiconductor die utilizing massreflow, thermocompression bonding (TCB), conductive epoxy, etc.

FIG. 1B provides an example illustration of various aspects of block220, for example die attachment aspects. For example, the first die 125(e.g., which may have been diced from a logic wafer prepared at block205) is electrically and mechanically attached the redistributionstructure 110. Similarly, the second die 126 (e.g., which may have beendiced from a logic wafer prepared at block 205) is electrically andmechanically attached to the redistribution structure 110. For example,as explained at block 205, the logic wafer (or die thereof) may havebeen prepared with various interconnection structures (e.g., conductivepads, lands, bumps, balls, wafer bumps, conductive pillars, etc.) formedthereon. Such structures are shown generally in FIG. 1B as items 119.Block 220 may, for example, comprise electrically and mechanicallyattaching such interconnection structures to the redistributionstructure 110 utilizing any of a variety of attachment processes (e.g.,mass reflow, thermocompression bonding (TCB), conductive epoxy, etc.).

The first die 125 and the second die 126 may comprise any of a varietyof die characteristics. In an example scenario, the first die 125 maycomprise a processor die and the second die 126 may comprise a memorydie. In another example scenario, the first die 125 may comprise aprocessor die, and the second die 126 may comprise a co-processor die.In another example scenario, the first die 125 may comprise a sensordie, and the second die 126 may comprise a sensor processing die. Thoughthe assembly 100 at FIG. 1B is shown with two die 125, 126, there may beany number of die. For example, there might be only one die, three die,four die, or more than four die.

Additionally, though the first die 125 and the second die 126 are shownattached to the redistribution structure 110 laterally relative to eachother, they may also be arranged in a vertical assembly. Variousnon-limiting examples of such structures are shown and discussed herein(e.g., die-on-die stacking, die attachment to opposite substrate sides,etc.). Also, though the first die 125 and the second die 126 are shownwith generally similar dimensions, such die 125, 126 may comprisedifferent respective characteristics (e.g., die height, footprint,connection pitch, etc.).

The first die 125 and the second die 126 are illustrated with generallyconsistent pitch, but this need not be the case. For example, most orall of the contacts 119 of the first die 125 in a region of the firstdie footprint immediately adjacent to the second die 126 and/or most ofthe contacts 119 of the second die 126 in a region of the second diefootprint immediately adjacent to the first die 125 may havesubstantially finer pitch than most or all of the other contacts 119.For example, a first 5, 10, or n rows of contacts 119 of the first die125 closest to the second die 126 (and/or of the second die 126 closestto the first die 125) may have a 30 micron pitch, while other contacts119 may generally have an 80 micron and/or 200 micron pitch. The RDstructure 110 may thus have corresponding contact structures and/ortraces at the corresponding pitch.

In general, block 220 comprises attaching one or more semiconductor dieto the redistribution structure (e.g., of a redistribution wafer).Accordingly, the scope of this disclosure should not be limited bycharacteristics of any particular die, or by characteristics of anyparticular multi-die layout, or by characteristics of any particularmanner of attaching such die, etc.

The example method 200 may, at block 225, comprise underfilling thesemiconductor die and/or other components attached to the RD structureat block 220. Block 225 may comprise performing such underfilling in anyof a variety of manners, non-limiting examples of which are presentedherein.

For example, after die attachment at block 220, block 225 may compriseunderfilling the semiconductor die utilizing a capillary underfill. Forexample, the underfill may comprise a reinforced polymer materialviscous enough to flow between the attached die and the RD wafer in acapillary action.

Also for example, block 225 may comprise underfilling the semiconductordie utilizing a non-conductive paste (NCP) and/or a non-conductive film(NCF) or tape while the die are being attached at block 220 (e.g.,utilizing a thermocompression bonding process). For example, suchunderfill materials may be deposited (e.g., printed, sprayed, etc.)prior to attaching the semiconductor die.

As with all of the blocks illustrated in the example method 200, block225 may be performed at any location in the method 200 flow so long asthe space between the die and the redistribution structure isaccessible.

The underfilling may also occur at a different block of the examplemethod 200. For example, the underfilling may be performed as part ofthe wafer molding block 230 (e.g., utilizing a molded underfill).

FIG. 1B provides an example illustration of various aspects of block225, for example the underfilling aspects. The underfill 128 ispositioned between the first semiconductor die 125 and theredistribution structure 110 and between the second semiconductor die126 and the redistribution structure 110, for example surrounding thecontacts 119.

Though the underfill 128 is generally illustrated to be flat, theunderfill may rise up and form fillets on the sides of the semiconductordie and/or other components. In an example scenario, at least a fourthor at least a half of the die side surfaces may be covered by theunderfill material. In another example scenario, one or more or all ofthe entire side surfaces may be covered by the underfill material. Alsofor example, a substantial portion of the space directly between thesemiconductor die, between the semiconductor die and other components,and/or between other components may be filled with the underfillmaterial. For example, at least half of the space or all of the spacebetween laterally adjacent semiconductor die, between the die and othercomponents, and/or between other components may be filled with theunderfill material. In an example implementation, the underfill 128 maycover the entire redistribution structure 110 of the RD wafer. In suchexample implementation, when the RD wafer is later diced, such dicingmay also cut through the underfill 128.

In general, block 225 may comprise underfilling the semiconductor dieand/or other components attached to the RD structure at block 220.Accordingly, the scope of this disclosure should not be limited bycharacteristics of any particular type of underfill or of any particularmanner of performing such underfilling.

The example method 200 may, at block 230, comprise molding the RD wafer(e.g., or an RD structure). Block 230 may comprise molding the RD waferin any of a variety of manners, non-limiting examples of which arepresented herein.

For example, block 230 may comprise molding over the top surface of theRD wafer, over the die and/or other components attached at block 220,over interconnection structures formed at block 215 (e.g., conductiveballs, ellipsoids, columns or pillars (e.g., plated pillars, wires orwirebond wires, etc.), etc.), over the underfill formed at block 225,etc.

Block 230 may, for example, comprise utilizing compression molding(e.g., utilizing liquid, powder and/or film) or vacuum molding. Also forexample, block 230 may comprise utilizing a transfer molding process(e.g., a wafer-level transfer molding process).

The molding material may, for example, comprise any of a variety ofcharacteristics. For example, the molding material (e.g., epoxy moldcompound (EMC), epoxy resin molding compound, etc.) may comprise arelatively high modulus, for example to provide wafer support in asubsequent process. Also for example, the molding material may comprisea relatively low modulus, to provide wafer flexibility in a subsequentprocess.

As explained herein, for example with regard to block 225, the moldingprocess of block 230 may provide underfill between the die and the RDwafer. In such an example, there may be uniformity of material betweenthe molded underfill material and the mold material encapsulating thesemiconductor die.

FIG. 1C provides an example illustration of various aspects of block230, for example molding aspects. For example, the molded assembly 100Cis shown with the mold material 130 covering the interconnectionstructures 121, first semiconductor die 125, second semiconductor die126, underfill 128, and the top surface of the redistribution structure110. Though the mold material 130, which may also be referred to hereinas encapsulant, is shown completely covering the sides and tops of thefirst semiconductor die 125 and second semiconductor die 126, this neednot be the case. For example, block 230 may comprise utilizing a filmassist or die seal molding technique to keep the die tops free of moldmaterial.

The mold material 130 may generally, for example, directly contact andcover portions of the die 125, 126 that are not covered by the underfill128. For example in a scenario in which at least a first portion of thesides of the die 125, 126 is covered by underfill 128, the mold material130 may directly contact and cover a second portion of the sides of thedie 125, 126. The mold material 130 may also, for example, fill thespace between the die 125, 126 (e.g., at least a portion of the spacethat is not already filled with underfill 128).

In general, block 230 may comprise molding the RD wafer. Accordingly,the scope of this disclosure should not be limited by characteristics ofany particular molding material, structure and/or technique.

The example method 200 may, at block 235, comprise grinding (orotherwise thinning) the mold material applied at block 230. Block 235may comprise grinding (or thinning) the mold material in any of avariety of manners, non-limiting examples of which are presented herein.

Block 235 may, for example, comprise mechanically grinding the moldmaterial to thin the mold material. Such thinning may, for example,leave the die and/or interconnection structures over molded, or suchthinning may expose one or more die and/or one or more interconnectionstructures.

Block 235 may, for example, comprise grinding other components inaddition to the mold compound. For example, block 235 may comprisegrinding the top sides (e.g., backsides or inactive sides) of the dieattached at block 220. Block 235 may also, for example, comprisegrinding the interconnect structures formed at block 215. Additionally,in a scenario in which the underfill applied at block 225 or block 230extends upward enough, block 235 may also comprise grinding suchunderfill material. Such grinding may, for example, result in a flatplanar surface at the top of the ground material.

Block 235 may, for example, be skipped in a scenario in which the heightof the mold material is originally formed at a desired thickness.

FIG. 1D provides an example illustration of various aspects of block235, for example the mold grinding aspects. The assembly 100D isillustrated with the mold material 130 (e.g., relative to the moldmaterial 130 illustrated at FIG. 1C) thinned to reveal top surfaces ofthe die 125, 126. In such an example, the die 125, 126 may also havebeen ground (or otherwise thinned).

Though as illustrated in FIG. 1D, the top surface of the mold materialis above the interconnection structures 121, and thus theinterconnection structures 121 were not ground, the interconnectionstructures 121 may be ground as well. Such an example implementationmay, for example, result in a top surface at this stage that includes atop surface of the die 125, 126, a top surface of the mold material 130,and a top surface of the interconnection structures 121, all in a commonplane.

As explained herein, the mold material 130 may be left covering the die125, 126 in an overmold configuration. For example, the mold material130 might not be ground, or the mold material 130 might be ground butnot to a height that exposes the die 125, 126.

In general, block 235 may comprise grinding (or otherwise thinning) themold material applied at block 230. Accordingly, the scope of thisdisclosure should not be limited by characteristics of any particularamount or type of grinding (or thinning).

The example method 200 may, at block 240, comprise ablating the moldmaterial applied at block 230. Block 240 may comprise ablating the moldmaterial in any of a variety of manners, non-limiting examples of whichare provided herein.

As discussed herein, the mold material may cover the interconnectionstructures formed at block 215. If the mold material covers theinterconnection structures and the interconnection structures need to berevealed (e.g., for subsequent package attachment, top-sideredistribution layer formation, top side laminate substrate attachment,electrical connection, heat sink connection, electromagnetic shieldconnection, etc.), block 240 may comprise ablating the mold material toreveal the connecting structures.

Block 240 may, for example, comprise exposing the interconnectionstructures through the mold material utilizing laser ablation. Also forexample, block 240 may comprise utilizing soft beam drilling, mechanicaldrilling, chemical drilling, etc.

FIG. 1D provides an example illustration of various aspects of block240, for example the ablation aspects. For example, the assembly 100D isshown comprising ablated vias 140 extending through the mold material130 to the interconnection structures 121. Though the ablated vias 140are shown with vertical side walls, it should be understood that thevias 140 may comprise any of a variety of shapes. For example the sidewalls may be sloped (e.g., with larger openings at the top surface ofthe mold material 130 than at the interconnection structure 121).

Though block 240 is illustrated in FIG. 2 as being immediately afterwafer molding at block 230 and mold grinding at block 235, block 240 maybe performed at any point later in the method 200. For example, block240 may be performed after the wafer support structure (e.g., attachedat block 245) is removed.

In general, block 240 may comprise ablating the mold material applied atblock 230 (e.g., to expose the interconnection structures formed atblock 215). Accordingly, the scope of this disclosure should not belimited by characteristics of any particular manner of performing suchablation or by characteristics of any particular ablated via structure.

The example method 200 may, at block 245, comprise attaching the moldedRD wafer (e.g., the top or mold side thereof) to a wafer supportstructure. Block 245 may comprise attaching the molded RD wafer to thewafer support structure in any of a variety of manners, non-limitingexamples of which are provided herein.

The wafer support structure may, for example, comprise a wafer orfixture formed of silicon, glass, or various other materials (e.g.,dielectric materials). Block 245 may, for example, comprise attachingthe molded RD wafer to the wafer support structure utilizing anadhesive, a vacuum fixture, etc. Note that as illustrated and explainedherein, a redistribution structure may be formed on the top side (orbackside) of the die and mold material prior to the wafer supportattachment.

FIG. 1E provides an example illustration of various aspects of block245, for example wafer support attaching aspects. The wafer supportstructure 150 is attached to the top side of the mold material 130 anddie 125, 126. The wafer support structure 150 may, for example, beattached with an adhesive, and such adhesive may also be formed in thevias 140 and contacting the interconnection structures 121. In anotherexample assembly, the adhesive does not enter the vias 140 and/or doesnot contact the interconnection structures 121. Note that in an assemblyin which the tops of the die 125, 126 are covered with the mold material130, the wafer support structure 150 might only be directly coupled tothe top of the mold material 130.

In general, block 245 may comprise attaching the molded RD wafer (e.g.,the top or mold side thereof) to a wafer support structure. Accordingly,the scope of this disclosure should not be limited by characteristics ofany particular type of wafer support structure or by characteristics ofany particular manner of attaching a wafer support structure.

The example method 200 may, at block 250, comprise removing a supportlayer from the RD wafer. Block 250 may comprise removing the supportlayer in any of a variety of manners, non-limiting examples of which arepresented herein.

As discussed herein, the RD wafer may comprise a support layer on whichan RD structure is formed and/or carried. The support layer may, forexample, comprise a semiconductor material (e.g., silicon). In anexample scenario in which the support layer comprises a silicon waferlayer, block 250 may comprise removing the silicon (e.g., removing allof the silicon from the RD wafer, removing almost all of the silicon,for example at least 90% or 95%, from the RD wafer, etc.). For example,block 250 may comprise mechanically grinding almost all of the silicon,followed by a dry or wet chemical etch to remove the remainder (oralmost all of the remainder). In an example scenario in which thesupport layer is loosely attached to the RD structure formed (orcarried) thereon, block 250 may comprise pulling or peeling to separatethe support layer from the RD structure.

FIG. 1F provides an example illustration of various aspects of block250, for example support layer removing aspects. For example, thesupport layer 105 (shown in FIG. 1E) is removed from the RD structure110. In the illustrated example, the RD structure 110 may still compriseabase dielectric layer 111 (e.g., an oxide, nitride, etc.) as discussedherein.

In general, block 250 may comprise removing a support layer from the RDwafer. Accordingly, the scope of this disclosure should not be limitedby characteristics of any particular type of wafer material or bycharacteristics of any particular manner of wafer material removal.

The example method 200 may, at block 255, comprise forming andpatterning a first redistribution layer (RDL) dielectric layer foretching an oxide layer of the RD structure. Block 255 may compriseforming and patterning the first RDL dielectric layer in any of avariety of manners, non-limiting examples of which are presented herein.

In the examples generally discussed herein, the RD structure of the RDwafer is generally formed on an oxide layer (or nitride or otherdielectric). To enable metal-to-metal attachment to the RD structureportions of the oxide layer covering traces (or pads or lands) of the RDstructure may be removed, for example by etching. Note that the oxidelayer need not necessarily be removed or completely removed so long asit has acceptable conductivity.

The first RDL dielectric layer may, for example, comprise a polyimide ora polybenzoxazole (PBO) material. The first RDL dielectric layer may,for example, comprise a laminated film or other materials. The first RDLdielectric layer may, for example, generally comprise an organicmaterial. In various example implementations, however, the first RDLdielectric layer may comprise an inorganic material.

In an example implementation, the first RDL dielectric layer maycomprise an organic material (e.g., polyimide, PBO, etc.) formed on afirst side of the base dielectric layer of the RD structure, which maycomprise an oxide or nitride or other dielectric material.

The first RDL dielectric layer may, for example, be utilized as a maskfor etching the base dielectric layer, for example an oxide or nitridelayer (e.g., at block 260). Also for example, after etching, the firstRDL dielectric layer may remain, for example to utilize in formingconductive RDL traces thereon.

In an alternative example scenario (not shown), a temporary mask layer(e.g., a temporary photoresist layer) may be utilized. For example,after etching, the temporary mask layer may be removed and replaced by apermanent RDL dielectric layer.

FIG. 1G provides an example illustration of various aspects of block255. For example, the first RDL dielectric layer 171 is formed andpatterned on the base dielectric layer 111. The patterned first RDLdielectric layer 171 may, for example, comprise vias 172 through thefirst RDL dielectric layer 171, for example through which the basedielectric layer 111 may be etched (e.g., at block 260) and in whichfirst traces (or portions thereof) may be formed (e.g., at block 265).

In general, block 255 may comprise forming and patterning a firstdielectric layer (e.g., a first RDL dielectric layer), for example onthe base dielectric layer. Accordingly, the scope of this disclosureshould not be limited by characteristics of a particular dielectriclayer or by characteristics of a particular manner of forming adielectric layer.

The example method 200 may, at block 260, comprise etching the basedielectric layer (e.g., oxide layer, nitride layer, etc.), for exampleunmasked portions thereof, from the RD structure. Block 260 may compriseperforming the etching in any of a variety of manners, non-limitingexamples of which are presented herein.

For example, block 260 may comprise performing a dry etch process (oralternatively a wet etch process) to etch through portions of the basedielectric layer (e.g., oxide, nitride, etc.) exposed by vias throughthe first dielectric layer, which functions as a mask for the etching.

FIG. 1G provides an example illustration of various aspects of block260, for example dielectric etching aspects. For example, portions ofthe base dielectric layer 111 that were shown below the first conductivetraces 112 in FIG. 1F are removed from FIG. 1G. This, for example,enables a metal-to-metal contact between the first conductive traces 112and first RDL traces formed at block 265.

In general, block 260 may, for example, comprise etching the basedielectric layer. Accordingly, the scope of this disclosure should notbe limited by any particular manner of performing such etching.

The example method 200 may, at block 265, comprise forming firstredistribution layer (RDL) traces. Block 265 may comprise forming thefirst RDL traces in any of a variety of manners, non-limiting examplesof which are presented herein.

As discussed herein, the first RDL dielectric layer (e.g., formed atblock 255) may be utilized for etching (e.g., at block 260) and thenremain for formation of the first RDL traces. Alternatively, the firstRDL dielectric layer may be formed and patterned after the etchingprocess. In yet another alternative implementation discussed herein, theetching process for the base dielectric layer may be skipped (e.g., inan implementation in which the base dielectric layer (e.g., a thin oxideor nitride layer) is conductive enough to adequately serve as aconductive path between metal traces.

Block 265 may comprise forming the first RDL traces attached to thefirst conductive traces of the RD structure that are exposed through thepatterned first RDL dielectric layer. The first RDL traces may also beformed on the first RDL dielectric layer. Block 265 may comprise formingthe first RDL traces in any of a variety of manners, for example byplating, but the scope of this disclosure is not limited by thecharacteristics of any particular manner of forming such traces.

The first RDL traces may comprise any of a variety of materials (e.g.,copper, gold, nickel, etc.). The first RDL traces may, for example,comprise any of a variety of dimensional characteristics. For example, atypical pitch for the first RDL traces may, for example, be 5 microns.In an example implementation, the first RDL traces may, for example, beformed at a center-to-center pitch that is approximately or at least anorder of magnitude greater than a pitch at which various traces of theRD structure of the RD wafer were formed (e.g., at a sub-micron pitch,approximately 0.5 micron pitch, etc.).

FIGS. 1G and 1H provide an example illustration of various aspects ofblock 265, for example RDL trace forming aspects. For example, a firstportion 181 of the first RDL traces may be formed in the vias 172 of thefirst RDL dielectric layer 171 and contacting the first conductivetraces 112 of the RD structure 110 exposed by such vias 172. Also forexample, a second portion 182 of the first RDL traces may be formed onthe first RDL dielectric layer 171.

In general, block 265 may comprise forming first redistribution layer(RDL) traces. Accordingly, the scope of this disclosure should not belimited by characteristics of any particular RDL traces or bycharacteristics of any particular manner of forming such RDL traces.

The example method 200 may, at block 270, comprise forming andpatterning a second RDL dielectric layer over the first RDL traces(e.g., formed at block 265) and the first RDL dielectric layer (e.g.,formed at block 255). Block 270 may comprise forming and patterning thesecond dielectric layer in any of a variety of manners, non-limitingexamples of which are presented herein.

For example, block 270 may share any or all characteristics with block255. The second RDL dielectric layer may, for example, be formedutilizing a same material as the first RDL dielectric layer formed atblock 255.

The second RDL dielectric layer may, for example, comprise a polyimideor a polybenzoxazole (PBO) material. The second RDL dielectric layermay, for example, generally comprise an organic material. In variousexample implementations, however, the first RDL dielectric layer maycomprise an inorganic material.

FIG. 1H provides an example illustration of various aspects of block270. For example, the second RDL dielectric layer 183 is formed on thefirst RDL traces 181, 182 and on the first RDL dielectric layer 171. Asshown in FIG. 1H, vias 184 are formed in the second RDL layer 183through which conductive contact can be made with the first RDL traces182 exposed by such vias 184.

In general, block 270 may comprise forming and/or patterning a secondRDL dielectric layer. Accordingly, the scope of this disclosure shouldnot be limited by characteristics of any particular dielectric layer orby characteristics of any particular manner of forming a dielectriclayer.

The example method 200 may, at block 275, comprise forming secondredistribution layer (RDL) traces. Block 275 may comprise forming thesecond RDL traces in any of a variety of manners, non-limiting examplesof which are presented herein. Block 275 may, for example, share any orall characteristics with block 265.

Block 275 may comprise forming the second RDL traces attached to thefirst RDL traces (e.g., formed at block 265) that are exposed throughvias in the patterned second RDL dielectric layer (e.g., formed at block270). The second RDL traces may also be formed on the second RDLdielectric layer. Block 275 may comprise forming the second RDL tracesin any of a variety of manners, for example by plating, but the scope ofthis disclosure is not limited by the characteristics of any particularmanner.

As with the first RDL traces, the second RDL traces may comprise any ofa variety of materials (e.g., copper, etc.). Additionally, the secondRDL traces may, for example, comprise any of a variety of dimensionalcharacteristics.

FIGS. 1H and 1I provide an example illustration of various aspects ofblock 275. For example, the second RDL traces 191 may be formed in vias184 in the second RDL dielectric layer 183 to contact the first RDLtraces 181 exposed through such vias 184. Additionally, the second RDLtraces 191 may be formed on the second RDL dielectric layer 183.

In general, block 275 may comprise forming second redistribution layer(RDL) traces. Accordingly, the scope of this disclosure should not belimited by characteristics of any particular RDL traces or bycharacteristics of any particular manner of forming such RDL traces

The example method 200 may, at block 280, comprise forming andpatterning a third RDL dielectric layer over the second RDL traces(e.g., formed at block 275) and the second RDL dielectric layer (e.g.,formed at block 270). Block 280 may comprise forming and patterning thethird dielectric layer in any of a variety of manners, non-limitingexamples of which are presented herein.

For example, block 280 may share any or all characteristics with blocks270 and 255. The third RDL dielectric layer may, for example, be formedutilizing a same material as the first RDL dielectric layer formed atblock 255 (and/or after etching at block 260 and stripping a temporarymask layer), and/or utilizing a same material as the second RDLdielectric layer formed at block 270.

The third RDL dielectric layer may, for example, comprise a polyimide ora polybenzoxazole (PBO) material. The third RDL dielectric layer may,for example, generally comprise an organic material. In various exampleimplementations, however, the third RDL dielectric layer may comprise aninorganic material.

FIG. 1I provides an example illustration of various aspects of block280. For example, the third RDL layer 185 may be formed on the secondRDL traces 191 and on the second RDL layer 183. As shown in FIG. 1I,vias are formed in the third RDL layer 185 through which conductivecontact can be made with the second RDL traces 191 exposed by such vias.

In general, block 280 may comprise forming and/or patterning a third RDLdielectric layer. Accordingly, the scope of this disclosure should notbe limited by characteristics of any particular dielectric layer or bycharacteristics of any particular manner of forming a dielectric layer.

The example method 200 may, at block 285, comprise forminginterconnection structures on the second RDL traces and/or on the thirdRDL dielectric layer. Block 285 may comprise forming the interconnectionstructures in any of a variety of manners, non-limiting examples ofwhich are presented herein.

Block 285 may, for example, comprise forming an underbump metal onportions of the second RDL traces exposed through vias in the thirddielectric layer. Block 285 may then, for example, comprise attachingconductive bumps or balls to the underbump metal. Other interconnectionstructures may be utilized as well, examples of which are presentedherein (e.g., conductive posts or pillars, solder balls, solder bumps,etc.).

FIG. 1I provides an example illustration of various aspects of block285, for example interconnection structure forming aspects. For example,interconnection structures 192 are attached to the second RDL traces 191through vias formed in the third RDL dielectric layer 185. Note thatalthough the interconnection structures 192 are illustrated as beingsmaller than the interconnection structures 121, this disclosure is notso limited. For example, the interconnection structures 192 may be thesame size as the interconnection structures 121 or larger than theinterconnection structures 121. Additionally, the interconnectionstructures 192 may be the same type of interconnection structure as theinterconnections structures 121 or may be a different type.

Though the redistribution layer(s) formed at blocks 255-285, which mayalso be referred to as the frontside redistribution layer (RDL), aregenerally illustrated in FIG. 1 in a fan-out assembly (e.g., extendingoutside of the footprint of the die 125, 126), they may also be formedin a fan-in assembly, for example in which the interconnectionstructures 192 do not generally extend outside the footprint of the die125, 126. Non-limiting examples of such an assembly are presentedherein.

In general, block 285 may comprise forming interconnection structures,for example on the second RDL traces and/or on the third RDL dielectriclayer. Accordingly, the scope of this disclosure should not be limitedby characteristics of any particular interconnection structures or byany particular manner of forming interconnection structures.

The example method 200 may, at block 290, comprise debonding (orde-attaching) the wafer support that was attached at block 245. Block290 may comprise performing such debonding in any of a variety ofmanners, non-limiting aspects of which are presented herein.

For example, in an example scenario in which the wafer support isadhesively attached, the adhesive may be released (e.g., using heatand/or force). Also for example, chemical release agents may beutilized. In another example scenario in which the wafer support isattached utilizing a vacuum force, the vacuum force may be released.Note that in a scenario involving adhesives or other substances to aidin the wafer support attachment, block 285 may comprise cleaning residuefrom the electrical assembly and/or from the wafer support after thedebonding.

FIGS. 1I and 1J provide an example illustration of various aspects ofblock 290. For example, the wafer support 150 illustrated in FIG. 1I isremoved in FIG. 1J.

In general, block 290 may comprise debonding the wafer support.Accordingly, the scope of this disclosure should not be limited bycharacteristics of any particular type of wafer support or by anyparticular manner of debonding a wafer support.

The example method 200 may, at block 295, comprise dicing the wafer.Block 295 may comprise dicing the wafer in any of a variety of manners,non-limiting examples of which are presented herein.

The discussion herein has generally focused on processing of a singledie of the RD wafer. Such focus on a single die of the RD wafer is forillustrative clarity only. It should be understood that all of theprocess steps discussed herein may be performed on an entire wafer. Forexample, each of the illustrations provided at FIGS. 1A-1J and otherfigures herein may be replicated tens or hundreds of times on a singlewafer. For example, until dicing, there might be no separation betweenone of the illustrated assemblies and a neighboring assembly of thewafer.

Block 295 may, for example, comprise dicing (e.g., mechanicalpunch-cutting, mechanical saw-cutting, later cutting, soft beam cutting,plasma cutting, etc.) the individual packages from the wafer. The endresult of such dicing may, for example, be the package shown in FIG. 1J.For example, the dicing may form side surfaces of the package comprisingcoplanar side surfaces of a plurality of components of the package. Forexample, side surfaces of any or all of the mold material 130, the RDstructure 110 dielectric layers, the various RDL dielectric layers,underfill 128, etc., may be coplanar.

In general, block 295 may comprise dicing the wafer. Accordingly, thescope of this disclosure should not be limited by characteristics of anyparticular manner of dicing a wafer.

FIGS. 1 and 2 presented various example method aspects and variationsthereof. Other example method aspects will now be presented withreference to additional figures.

As discussed herein in the discussion of FIGS. 1 and 2 , block 235 maycomprise grinding (or otherwise thinning) the mold material 130 toexpose one or more of the die 125, 126. An example is provided at FIG.1D.

As also discussed, the mold grinding (or thinning) at block 235 need notbe performed or may be performed to an extent that still leaves the topsof the die 125, 126 covered with mold material 130. An example isprovided at FIG. 3 . As shown in FIG. 3A, the mold material 130 coversthe tops of the semiconductor die 125, 126. Note that theinterconnection structures 121 may be shorter or taller than the die125, 126. Continuing the comparison, rather than the resulting package100J appearing as shown in FIG. 1J, the resulting package 300B mayappear as shown in FIG. 3B.

Also, as discussed herein in the discussion of FIGS. 1 and 2 , block215, forming TMV interconnection structures, and block 240, TMV moldablation, may be skipped. An example is provided at FIG. 4 . As shown inFIG. 4A, as opposed to block 215 and FIG. 1B, there are no TMVinterconnection structures 121 formed. As shown in FIG. 4B, as opposedto block 230 and FIG. 1C, the mold material 130 does not coverinterconnection structures.

Continuing the comparison, as explained herein, the mold grinding (orthinning) at block 235 may be performed to an extent that exposes one ormore of the tops of the die 125, 126 from the mold material 130. FIG. 4Cprovides an example illustration of such processing. Generally, the FIG.4C assembly 400C is similar to the FIG. 1J assembly 100J, less theinterconnection structures 121 and the ablated vias exposing theinterconnection structures through the mold material 130.

Also for example, as explained herein, the mold grinding (or thinning)at block 235 may be skipped or performed to an extent that leaves thetops of the die 125, 126 covered with mold material 130. FIG. 4Dprovides an example illustration of such processing. Generally, the FIG.4D assembly 400D is similar to the FIG. 1J assembly 100J, less theinterconnection structures 121 and the ablated vias exposing theinterconnection structures through the mold material 130, and with moldmaterial 130 covering the die 125, 126.

In another example, as explained herein in the discussion of block 215,the TMV interconnections may comprise any of a variety of structures,for example a conductive pillar (e.g., plated post or pillar, verticalwire, etc.). FIG. 5A provides an example illustration of conductivepillars 521 attached to the RD structure 110. The conductive pillars 521may, for example, be plated on the RD structure 110. The conductivepillars 521 may also, for example, comprise wires (e.g., wire-bondwires) attached (e.g., wire-bond attached, soldered, etc.) to the RDstructure 110 and extending vertically. The conductive pillars 521 may,for example, extend from the RD structure 110 to a height greater than aheight of the die 125, 126, equal to the height of one or more of thedie 125, 126, less than a height of the die 125, 126, etc. In an exampleimplementation, the pillars may have a height greater than or equal to200 microns at a center-to-center pitch of 100-150 microns. Note thatany number of rows of the pillars 521 may be formed. Generally, the FIG.5A assembly 500A is similar to the FIG. 1B assembly 100B with conductivepillars 521 as interconnection structures instead of conductive balls121.

Continuing the example, FIG. 5B illustrates the RD structure 110,conductive pillars 521, semiconductor die 125, 126, and underfill 128covered with mold material 130. The molding may, for example, beperformed in accordance with block 230 of the example method 200.Generally, the FIG. 5B assembly 500B is similar to the FIG. 1C assembly100C with conductive pillars 521 as interconnection structures insteadof conductive balls 121.

Still continuing the example, FIG. 5C illustrates the mold material 130having been thinned (e.g., ground) to a desired thickness. The thinningmay, for example, be performed in accordance with block 235 of theexample method 200. Note, for example, that the conductive pillars 521and/or the semiconductor die 125, 126 may also be thinned. Generally,the FIG. 5D assembly 500D is similar to the FIG. 1D assembly 100D withconductive pillars 521 as interconnection structures instead ofconductive balls 121, and also without the ablated vias 140 of FIG. 1D.For example, the thinning of the mold material 130 may expose the topends of the conductive pillars 521. If instead, however, the thinning ofthe mold material 130 does not expose the top ends of the conductivepillars 521, a mold ablating operation (e.g., in accordance with block240) may be performed. Note that although the assembly is shown with thetops of the semiconductor die 125, 126 being exposed, the tops need notbe exposed. For example, the pillars 521 may stand taller than thesemiconductor die 125, 126. Such an example configuration may, forexample allow the pillars 521 to be exposed from and/or protrude fromthe mold material 130 while the mold material 130 continues to cover thebackside surfaces of the semiconductor die 125, 126, which may, forexample, provide protection for the semiconductor die 125, 126, preventor reduce warpage, etc.

In an example implementation in which the pillars 521 are formed with aheight less than the die 125, 126, the thinning may comprise firstgrinding the mold material 130, then grinding both the mold material 130and the back (or inactive) sides of the die 125, 126 until the pillars521 are exposed. At this point, the thinning may be stopped or may becontinued, for example grinding the mold material 130, the die 125, 126and the pillars 521.

Continuing the example, the assembly 500C shown in FIG. 5C may befurther processed by forming a redistribution layer (RDL) 532 over themold material 130 and die 125, 126. FIG. 5D shows an example of suchprocessing. The redistribution layer 532 may also be referred to hereinas the backside redistribution (RDL) layer 532. Though such backside RDLformation is not explicitly shown in one of the blocks of the examplemethod 200, such operation may be performed in any of the blocks, forexample after the block 235 mold grinding operation and before the block245 wafer support attaching (e.g., at block 235, at block 240, at block245, or between any of such blocks).

As shown in FIG. 5D, a first backside dielectric layer 533 may be formedand patterned on the mold material 130 and the die 125, 126. The firstbackside dielectric layer 533 may, for example, be formed and patternedin a same or similar manner to the first RDL dielectric layer 171 formedat block 260, albeit on a different surface. For example, the firstbackside dielectric layer 533 may be formed on the mold material 130 andon the semiconductor die 125, 126 (e.g., directly on exposed backsidesurfaces of the die 125, 126, on mold material 130 covering the backsidesurfaces of the die 125, 126, etc.), and vias 534 may be formed (e.g.,by etching, ablating, etc.) in the first backside dielectric layer 533to expose at least the tops of the conductive pillars 521. Note that inan example configuration in which the mold material 130 covers thebackside surfaces of the semiconductor die 125, 126, the first backsidedielectric layer 533 may still be formed, but need not be (e.g., thebackside traces 535 discussed below may be formed directly on the moldmaterial 130 rather than on the first backside dielectric layer 533).

Backside traces 535 may be formed on the first backside dielectric layer533 and in the vias 534 of the first backside dielectric layer 533. Thebackside traces 535 may thus be electrically connected to the conductivepillars 521. The backside traces 535 may, for example, be formed in asame or similar manner to the first RDL traces formed at block 265. Atleast some, if not all, of the backside traces 535 may, for example,extend horizontally from the conductive pillars 521 to locationsdirectly above the semiconductor die 125, 126. At least some of thebackside traces 535 may also, for example, extend from the conductivepillars 521 to locations that are not directly above the semiconductordie 125, 126.

A second backside dielectric layer 536 may be formed and patterned onthe first backside dielectric layer 533 and backside traces 535. Thesecond backside dielectric layer 536 may, for example, be formed andpatterned in a same or similar manner to the second RDL dielectric layer183 formed at block 270, albeit on a different surface. For example, thesecond backside dielectric layer 536 may be formed over the firstbackside dielectric layer 533 and over the backside traces 535 and vias537 may be formed (e.g., by etching, ablating, etc.) in the secondbackside dielectric layer 536 to expose contact areas of the backsidetraces 535.

Backside interconnection pads 538 (e.g., ball contact pads) may beformed on the second backside dielectric layer 536 and/or in the vias537 of the second backside dielectric layer 536. The backsideinterconnection pads 538 may thus be electrically connected to thebackside traces 535. The backside interconnection pads 538 may, forexample, be formed in a same or similar manner to the second RDL tracesformed at block 275. The backside interconnection pads 538 may, forexample, be formed by forming metal contact pads and/or forming underbump metallization (e.g., to enhance subsequent attachment to thebackside traces 535 by interconnection structures).

Though the backside RDL layer 532 is shown with two backside dielectriclayers 533, 536 and one layer of backside traces 535, it should beunderstood that any number of dielectric and/or trace layers may beformed.

As shown by example in FIG. 5E, after the backside RDL layer 532 isformed, a wafer support structure 150 may be attached to the backsideRDL layer 532 (e.g., directly, with an intervening adhesive layer,utilizing vacuum force, etc.). The wafer support 150 may, for example,be attached in a same or similar manner to the wafer support 150attached at block 245. For example, FIG. 5E shows the wafer support 150attachment in a manner similar to that of FIG. 1E, albeit withattachment to the RDL layer 532 rather than attachment to the mold layer130 and semiconductor die 125, 126.

As illustrated by example in FIG. 5F, the support layer 105 (shown inFIG. 5E) may be removed from the RD wafer, a frontside redistributionlayer may be formed on a side of the RD structure 110 opposite the die125, 126, interconnection structures 192 may be formed, and the wafersupport 150 may be removed.

For example, the support layer 105 may be removed in a same or similarmanner to that discussed herein with regard to block 250 and FIGS.1E-1F. Also for example, a frontside redistribution layer may be formedin a same or similar manner to that discussed herein with regard toblocks 255-280 and FIGS. 1G-1H. Additionally for example,interconnection structures 192 may be formed in a same or similar mannerto that discussed herein with regard to block 285 and FIG. 1I. Furtherfor example, the wafer support 150 may be removed in a same or similarmanner to that discussed herein with regard to block 290 and FIG. 1J.

In another example implementation, a substrate (e.g., a laminatesubstrate, package substrate, etc.) may be attached above thesemiconductor die 125, 126, for example instead of or in addition to thebackside RDL discussed herein with regard to FIG. 5 . For example, asillustrated in FIG. 6A, the interconnection structures 621 may be formedat a height that will extend to the height of the die 125, 126. Notethat this height is not necessarily present, for example in a scenarioin which the backside substrate has its own interconnection structuresor in which additional interconnection structures are utilized betweenthe interconnection structures 621 and the backside substrate. Theinterconnection structures 621 may, for example, be attached in a sameor similar manner as that discussed herein with regard to block 215 andFIG. 1B.

Continuing the example, as illustrated in FIG. 6B, the assembly 600B maybe molded and the mold may be thinned if necessary. Such molding and/orthinning may, for example, be performed in a same or similar manner tothat discussed herein with regard to blocks 230 and 235, and FIGS. 1Cand 1D.

As shown in FIG. 6C, a wafer support 150 may be attached, support layer105 may be removed, and a front side RDL may be formed. For example, awafer support 150 may be attached in a same or similar manner as thatdiscussed herein with regard to block 245 and FIG. 1E. Also for example,support layer 105 may be removed in a same or similar manner as thatdiscussed herein with regard to block 250 and FIG. 1F. Additionally forexample, a frontside RDL may be formed in a same or similar manner asthat discussed herein with regard to blocks 255-280 and FIGS. 1G-1H.

As illustrated in FIG. 6D, interconnection structures 192 may beattached, the wafer support 150 may be removed, and the backsidesubstrate 632 may be attached. For example, the interconnectionstructures 192 may be attached in a same or similar manner as thatdiscussed herein with regard to block 285 and FIG. 1I. Also for example,the wafer support 150 may be removed in a same or similar manner as thatdiscussed herein with regard to block 290 and FIG. 1J. Further forexample, the backside substrate 632 may be electrically attached to theinterconnection structures 621 and/or mechanically attached to the moldmaterial 130 and/or the die 125, 126. The backside substrate 632 may,for example, be attached in wafer (or panel) form and/or single packageform, and may for example be attached before or after dicing (e.g., asdiscussed at block 295).

The example methods and assemblies shown in FIGS. 1-7 and discussedherein are merely non-limiting examples presented to illustrate variousaspects of this disclosure. Such methods and assemblies may also shareany or all characteristics with the methods and assemblies shown anddiscussed in the following co-pending United States patent applications:U.S. patent application Ser. No. 13/753,120, filed Jan. 29, 2013, andtitled “SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTORDEVICE”; U.S. patent application Ser. No. 13/863,457, filed on Apr. 16,2013, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHODTHEREOF”; U.S. patent application Ser. No. 14/083,779, filed on Nov. 19,2013, and titled “SEMICONDUCTOR DEVICE WITH THROUGH-SILICON VIA-LESSDEEP WELLS”; U.S. patent application Ser. No. 14/218,265, filed Mar. 18,2014, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHODTHEREOF”; U.S. patent application Ser. No. 14/313,724, filed Jun. 24,2014, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHODTHEREOF”; U.S. patent application Ser. No. 14/444,450, Jul. 28, 2014,and titled “SEMICONDUCTOR DEVICE WITH THIN REDISTRIBUTION LAYERS”; U.S.patent application Ser. No. 14/524,443, filed Oct. 27, 2014, and titled“SEMICONDUCTOR DEVICE WITH REDUCED THICKNESS”; U.S. patent applicationSer. No. 14/532,532, filed Nov. 4, 2014, and titled “INTERPOSER,MANUFACTURING METHOD THEREOF, SEMICONDUCTOR PACKAGE USING THE SAME, ANDMETHOD FOR FABRICATING THE SEMICONDUCTOR PACKAGE”; U.S. patentapplication Ser. No. 14/546,484, filed Nov. 18, 2014, and titled“SEMICONDUCTOR DEVICE WITH REDUCED WARPAGE”; and U.S. patent applicationSer. No. 14/671,095, filed Mar. 27, 2015, and titled “SEMICONDUCTORDEVICE AND MANUFACTURING METHOD THEREOF;” the contents of each of whichare hereby incorporated herein by reference in their entirety.

It should be noted that any or all of the semiconductor packagesdiscussed herein may be, but need not be, attached to a packagesubstrate. Various non-limiting examples of such semiconductor devicepackages and methods of manufacturing thereof will now be discussed.

FIGS. 7A-7L show cross-sectional views illustrating an examplesemiconductor package and an example method of making a semiconductorpackage, in accordance with various aspects of the present disclosure.The structures shown in 7A-7L may, for example, share any or allcharacteristics with analogous structures shown in FIGS. 1A-1J, 3A-3B,4A-4D, 5A-5F, 6A-6D, 9, 10A-10B, 11A-11D, 12A-12B, 13, and 14 . FIG. 8is a flow diagram of an example method 800 of making a semiconductorpackage, in accordance with various aspects of the present disclosure.The example method 800 may, for example, share any or allcharacteristics with the example method 200 illustrated in FIG. 2 anddiscussed herein and with any methods discussed herein. FIGS. 7A-7L may,for example, illustrate an example semiconductor package at varioussteps (or blocks) of the production method 800 of FIG. 8 . FIGS. 7A-7Land FIG. 8 will now be discussed together.

The example method 800 may, at block 805, comprise preparing a logicwafer for processing (e.g., for packaging). Block 805 may comprisepreparing a logic wafer for processing in any of a variety of manners,non-limiting examples of which are presented herein. Block 805 may, forexample, share any or all characteristics with block 205 of the examplemethod 200 shown in FIG. 2 and discussed herein.

The example method 800 may, at block 810, comprise preparing aredistribution structure wafer (RD wafer). Block 810 may comprisepreparing an RD wafer for processing in any of a variety of manners,non-limiting examples of which are provided herein. Block 810 may, forexample, share any or all characteristics with block 210 of the examplemethod 200 shown in FIG. 2 and discussed herein.

FIG. 7A provides an example illustration of various aspects of block810. Referring to FIG. 7A, the RD wafer 700A may, for example, comprisea support layer 705 (e.g., a silicon layer). A redistribution (RD)structure 710 may be formed on the support layer 105. The RD structure710 may, for example, comprise a base dielectric layer 711, a firstdielectric layer 713, first conductive traces 712, a second dielectriclayer 716, second conductive traces 715, and interconnection structures717.

The base dielectric layer 711 may, for example, be on the support layer705. The base dielectric layer 711 may, for example, comprise an oxidelayer, a nitride layer, etc. The base dielectric layer 711 may, forexample, be formed to specification and/or may be native.

The RD wafer 700A may also, for example, comprise first conductivetraces 712 and a first dielectric layer 713. The first conductive traces712 may, for example, comprise deposited conductive metal (e.g., copper,etc.). The first dielectric layer 713 may, for example, comprise aninorganic dielectric material (e.g., silicon oxide, silicon nitride,etc.). In an alternative assembly, the first dielectric layer 713 maycomprise an organic dielectric material.

The RD wafer 700A may also, for example, comprise second conductivetraces 715 and a second dielectric layer 716. The second conductivetraces 715 may, for example, comprise deposited conductive metal (e.g.,copper, etc.). The second conductive traces 715 may, for example, beconnected to respective first conductive traces 712 through respectiveconductive vias 714 (e.g., in the first dielectric layer 713). Thesecond dielectric layer 716 may, for example, comprise an inorganicdielectric material (e.g., silicon oxide, silicon nitride, etc.). In analternative assembly, the second dielectric layer 716 may comprise anorganic dielectric material.

Though two sets of dielectric layers and conductive traces areillustrated in FIG. 7A, it should be understood that the RD structure710 of the RD wafer 700A may comprise any number of such layers andtraces. For example, the RD structure 710 might comprise only onedielectric layer and/or set of conductive traces, three sets ofdielectric layers and/or conductive traces, etc.

As with the logic wafer prep at block 205, block 210 may compriseforming interconnection structures (e.g., conductive bumps, conductiveballs, conductive pillars, conductive lands or pads, etc.) on a surfaceof the RD structure 710. Examples of such interconnection structures 717are shown in FIG. 7A, in which the RD structure 710 comprisesinterconnection structures 717, which are shown formed on the front (ortop) side of the RD structure 710 and electrically connected torespective second conductive traces 715 through conductive vias in thesecond dielectric layer 716. Such interconnection structures 717 may,for example, be utilized to couple the RD structure 710 to variouselectronic components (e.g., active semiconductor components or die,passive components, etc.).

The interconnection structures 717 may, for example, comprise any of avariety of conductive materials (e.g., any one of or a combination ofcopper, nickel, gold, etc.). The interconnection structures 717 mayalso, for example, comprise solder.

In general, block 810 may comprise preparing a redistribution structurewafer (RD wafer). Accordingly, the scope of this disclosure should notbe limited by characteristics of any particular manner of performingsuch preparing.

The example method 800 may, at block 820, comprise attaching one or moresemiconductor die to the RD structure (e.g., of the RD wafer). Block 820may comprise attaching the die to the RD structure in any of a varietyof manners, non-limiting examples of which are provided herein. Block820 may, for example, share any or all characteristics with block 220 ofthe example method 200 shown in FIG. 2 and discussed herein.

FIG. 7B provides an example illustration of various aspects of block820, for example the die attachment. For example, the first die 725(e.g., which may have been diced from a logic wafer prepared at block805) is electrically and mechanically attached to the redistributionstructure 710. Similarly, the second die 726 (e.g., which may have beendiced from a logic wafer prepared at block 805) is electrically andmechanically attached to the redistribution structure 710.

The first die 725 and the second die 726 may comprise any of a varietyof die characteristics. In an example scenario, the first die 725 maycomprise a processor die and the second die 726 may comprise a memorydie. In another example scenario, the first die 725 may comprise aprocessor die, and the second die 726 may comprise a co-processor die.In another example scenario, the first die 725 may comprise a sensordie, and the second die 726 may comprise a sensor processing die. Thoughthe assembly 700B at FIG. 7B is shown with two die 725, 726, there maybe any number of die. For example, there might be only one die, threedie, four die, or more than four die.

Additionally, though the first die 725 and the second die 726 are shownattached to the redistribution structure 710 laterally relative to eachother, they may also be arranged in a vertical assembly. Variousnon-limiting example assemblies of such structures are shown anddiscussed herein (e.g., die-on-die stacking, die attach to oppositesubstrate side, etc.). Also, though the first die 725 and the second die726 are shown with generally similar dimensions, such die 725, 726 maycomprise different respective characteristics (e.g., die height,footprint, connection pitch, etc.).

The first die 725 and the second die 726 are illustrated with generallyconsistent pitch, but this need not be the case. For example, most orall of the contacts of the first die 725 in a region of the first diefootprint immediately adjacent to the second die 726 and/or most of thecontacts of the second die 726 in a region of the second die footprintimmediately adjacent to the first die 725 may have substantially finerpitch than most or all of the other contacts. For example, a first 5,10, or n rows of contacts of the first die 725 closest to the second die726 (and/or of the second die 726 closest to the first die 725) may havea 30 micron pitch, while other contacts may generally have an 80 micronand/or 200 micron pitch. The RD structure 710 may thus havecorresponding contact structures and/or traces at the correspondingpitch.

In general, block 820 comprises attaching one or more semiconductor dieto the redistribution structure (e.g., of a redistribution wafer).Accordingly, the scope of this disclosure should not be limited bycharacteristics of any particular die or by characteristics of anyparticular multi-die layout, or by characteristics of any particularmanner of attaching such die, etc.

The example method 800 may, at block 825, comprise underfilling thesemiconductor die and/or other components attached to the RD structureat block 820. Block 825 may comprise performing such underfilling in anyof a variety of manners, non-limiting examples of which are presentedherein. Block 825 may, for example, share any or all characteristicswith block 225 of the example method 200 shown in FIG. 2 and discussedherein.

FIG. 7B provides an example illustration of various aspects of block825, for example the underfilling. The underfill 728 is positionedbetween the first semiconductor die 725 and the redistribution structure710 and between the second semiconductor die 726 and the redistributionstructure 710.

Though the underfill 728 is generally illustrated to be flat, theunderfill may rise up and form fillets on the sides of the semiconductordie and/or other components. In an example scenario, at least a fourthor at least a half of the die side surfaces may be covered by theunderfill material. In another example scenario, one or more or all ofthe entire side surfaces may be covered by the underfill material. Alsofor example, a substantial portion of the space directly between thesemiconductor die, between the semiconductor die and other components,and/or between other components may be filled with the underfillmaterial. For example, at least half of the space or all of the spacebetween laterally adjacent semiconductor die, between the semiconductordie and other components, and/or between other components may be filledwith the underfill material. In an example implementation, the underfill728 may cover the entire redistribution structure 710 of the RD wafer.In such example implementation, when the RD wafer is later diced, suchdicing may also cut through the underfill 728.

In general, block 825 may comprise underfilling the semiconductor dieand/or other components attached to the RD structure at block 820.Accordingly, the scope of this disclosure should not be limited bycharacteristics of any particular type of underfill or of any particularmanner of performing such underfilling.

The example method 800 may, at block 830, comprise molding the RD wafer(or RD structure). Block 830 may comprise molding the RD wafer in any ofa variety of manners, non-limiting examples of which are presentedherein. Block 830 may, for example, share any or all characteristicswith block 230 of the example method 200 shown in FIG. 2 and discussedherein.

FIG. 7C provides an example illustration of various aspects of block830, for example molding aspects. For example, the molded assembly 700Cis shown with the mold material 730 covering the first semiconductor die725, second semiconductor die 726, underfill 728, and the top surface ofthe redistribution structure 710. Though the mold material 730, whichmay also be referred to herein as encapsulant, is shown completelycovering the sides and tops of the first semiconductor die 725 andsecond semiconductor die 726, this need not be the case. For example,block 830 may comprise utilizing a film assist or die seal moldingtechnique to keep the die tops free of mold material.

The mold material 730 may generally, for example, directly contact andcover portions of the die 725, 726 that are not covered by the underfill728. For example in a scenario in which at least a first portion of thesides of the die 725, 726 is covered by underfill 728, the mold material730 may directly contact and cover a second portion of the sides of thedie 725, 726. The mold material 730 may also, for example, fill thespace between the die 725, 726 (e.g., at least a portion of the spacethat is not already filled with underfill 728).

In general, block 830 may comprise molding the RD wafer. Accordingly,the scope of this disclosure should not be limited by characteristics ofany particular molding material, structure and/or technique.

The example method 800 may, at block 835, comprise grinding (orotherwise thinning) the mold material applied at block 830. Block 835may comprise grinding (or thinning) the mold material in any of avariety of manners, non-limiting examples of which are presented herein.Block 835 may, for example, share any or all characteristics with block235 of the example method 200 shown in FIG. 2 and discussed herein.

FIG. 7D provides an example illustration of various aspects of block835, for example the mold grinding aspects. The assembly 700D isillustrated with the mold material 730 (e.g., relative to the moldmaterial 730 illustrated at FIG. 7C) thinned to reveal top surfaces ofthe die 725, 726. In such an example, the die 725, 726 may also havebeen ground (or otherwise thinned).

As explained herein, the mold material 730 may be left covering the die725, 726 in an overmold assembly. For example, the mold material 730might not be ground, or the mold material 730 might be ground but not toa height that exposes the die 725, 726.

In general, block 835 may comprise grinding (or otherwise thinning) themold material applied at block 830. Accordingly, the scope of thisdisclosure should not be limited by characteristics of any particularamount or type of grinding (or thinning).

The example method 800 may, at block 845, comprise attaching the moldedRD wafer (e.g., the top or mold side thereof) to a wafer supportstructure. Block 845 may comprise attaching the molded RD wafer to thewafer support structure in any of a variety of manners, non-limitingexamples of which are provided herein. Block 845 may, for example, shareany or all characteristics with block 245 of the example method 200shown in FIG. 2 and discussed herein.

FIG. 7E provides an example illustration of various aspects of block845, for example wafer support attaching aspects. The wafer supportstructure 750 is attached to the top side of the mold material 730 anddie 725, 726. The wafer support structure 750 may, for example, beattached with an adhesive. Note that in an assembly in which the tops ofthe die 725, 726 are covered with the mold material 730, the wafersupport structure 750 might only be directly coupled to the top of themold material 730.

In general, block 845 may comprise attaching the molded RD wafer (e.g.,the top or mold side thereof) to a wafer support structure. Accordingly,the scope of this disclosure should not be limited by characteristics ofany particular type of wafer support structure or by characteristics ofany particular manner of attaching a wafer support structure.

The example method 200 may, at block 850, comprise removing a supportlayer from the RD wafer. Block 850 may comprise removing the supportlayer in any of a variety of manners, non-limiting examples of which arepresented herein. Block 850 may, for example, share any or allcharacteristics with block 250 of the example method 200 shown in FIG. 2and discussed herein.

As discussed herein, the RD wafer may comprise a support layer on whichan RD structure is formed and/or carried. The support layer may, forexample, comprise a semiconductor material (e.g., silicon). In anexample scenario in which the support layer comprises a silicon waferlayer, block 850 may comprise removing the silicon (e.g., removing allof the silicon from the RD wafer, removing almost all of the silicon,for example at least 90% or 95%, from the RD wafer, etc.). For example,block 850 may comprise mechanically grinding almost all of the silicon,followed by a dry or wet chemical etch to remove the remainder (oralmost all of the remainder). In an example scenario in which thesupport layer is loosely attached to the RD structure formed (orcarried) thereon, block 850 may comprise pulling or peeling to separatethe support layer from the RD structure.

FIG. 7F provides an example illustration of various aspects of block850, for example support layer removing aspects. For example, thesupport layer 705 (shown in FIG. 7E) is removed from the RD structure710. In the illustrated example, the RD structure 710 may still compriseabase dielectric layer 711 (e.g., an oxide, nitride, etc.) as discussedherein.

In general, block 850 may comprise removing a support layer from the RDwafer. Accordingly, the scope of this disclosure should not be limitedby characteristics of any particular type of wafer material or bycharacteristics of any particular manner of wafer material removal.

The example method 800 may, at block 855, comprise forming andpatterning a redistribution layer (RDL) dielectric layer for etching anoxide layer of the RD structure. Block 855 may comprise forming andpatterning the RDL dielectric layer in any of a variety of manners,non-limiting examples of which are presented herein. Block 855 may, forexample, share any or all characteristics with block 255 of the examplemethod 200 shown in FIG. 2 and discussed herein.

FIG. 7G provides an example illustration of various aspects of block855. For example, the RDL dielectric layer 771 is formed and patternedon the base dielectric layer 711. The patterned RDL dielectric layer 771may, for example, comprise vias 772 through the RDL dielectric layer771, for example through which the base dielectric layer 711 may beetched (e.g., at block 860) and in which conductive traces (or portionsthereof) may be formed (e.g., at block 865).

In general, block 855 may comprise forming and patterning a dielectriclayer (e.g., an RDL dielectric layer), for example on the basedielectric layer. Accordingly, the scope of this disclosure should notbe limited by characteristics of a particular dielectric layer or bycharacteristics of a particular manner of forming a dielectric layer.

The example method 800 may, at block 860, comprise etching the basedielectric layer (e.g., oxide layer, nitride layer, etc.), for exampleunmasked portions thereof, from the RD structure. Block 860 may compriseperforming the etching in any of a variety of manners, non-limitingexamples of which are presented herein. Block 860 may, for example,share any or all characteristics with block 260 of the example method200 shown in FIG. 2 and discussed herein.

FIG. 7G provides an example illustration of various aspects of block860. For example, portions of the base dielectric layer 711 that wereshown below the first conductive traces 712 in FIG. 7F are removed fromFIG. 7G. This, for example, enables a metal-to-metal contact between thefirst conductive traces 712 and the RDL traces formed at block 865.

In general, block 860 may, for example, comprise etching the basedielectric layer. Accordingly, the scope of this disclosure should notbe limited by any particular manner of performing such etching.

The example method 800 may, at block 865, comprise formingredistribution layer (RDL) traces. Block 865 may comprise forming theRDL traces in any of a variety of manners, non-limiting examples ofwhich are presented herein. Block 865 may, for example, share any or allcharacteristics with block 265 of the example method 200 shown in FIG. 2and discussed herein.

FIGS. 7G and 7H provide an example illustration of various aspects ofblock 865, for example RDL trace forming aspects. For example, a firstportion 781 of the RDL traces may be formed in the vias 772 of the RDLdielectric layer 771 and contacting the first conductive traces 712 ofthe RD structure 710 exposed by such vias 772. Also for example, asecond portion 782 of the first RDL traces may be formed on the firstRDL dielectric layer 771.

In general, block 865 may comprise forming redistribution layer (RDL)traces. Accordingly, the scope of this disclosure should not be limitedby characteristics of any particular RDL traces or by characteristics ofany particular manner of forming such RDL traces.

Note that although the example method 800, shows the formation of onlyone RDL dielectric layer at 855 and one RDL trace layer at block 865,such blocks may be repeated as many times as desired.

The example method 800 may, at block 885, comprise forminginterconnection structures on the RDL traces. Block 885 may compriseforming the interconnection structures in any of a variety of manners,non-limiting examples of which are presented herein. For example, block885 may share any or all characteristics with block 285 of the examplemethod 200 shown in FIG. 2 and discussed herein.

Block 885 may, for example, comprise forming conductive pillars (e.g.,metal pillars, copper pillars, solder-capped pillars, etc.) and/orconductive bumps (e.g., solder bumps, etc.) on the RDL traces. Forexample, block 885 may comprise plating conductive pillars, placing orpasting conductive bumps, etc.

FIG. 7I provides an example illustration of various aspects of block885, for example bump forming aspects. For example, interconnectionstructures 792 (e.g., shown as solder-capped metal pillars, for examplecopper pillars) are attached to the RDL traces 782.

Though the redistribution layer(s) formed at blocks 855-885, which mayalso be referred to as the frontside redistribution layer (RDL), aregenerally illustrated in FIG. 7 in a fan-in assembly (e.g., generallycontained within the footprint of the die 725, 726), they may also beformed in a fan-out assembly, for example in which at least a portionthe interconnection structures 792 generally extend outside thefootprint of the die 125, 126. Non-limiting examples of such an assemblyare presented herein.

In general, block 885 may comprise forming interconnection structures,for example on the RDL traces and/or on the RDL dielectric layer.Accordingly, the scope of this disclosure should not be limited bycharacteristics of any particular interconnection structures or by anyparticular manner of forming interconnection structures.

The example method 800 may, at block 890, comprise debonding (orde-attaching) the wafer support that was attached at block 845. Block890 may comprise performing such debonding in any of a variety ofmanners, non-limiting examples of which are presented herein. Forexample, block 890 may share any or all characteristics with block 290of the example method 200 shown in FIG. 2 and discussed herein.

FIGS. 7H and 7I provide an example illustration of various aspects ofblock 890. For example, the wafer support 750 illustrated in FIG. 7H isremoved in FIG. 7I.

In general, block 890 may comprise debonding the wafer support.Accordingly, the scope of this disclosure should not be limited bycharacteristics of any particular type of wafer support or by anyparticular manner of debonding a wafer support.

The example method 800 may, at block 895, comprise dicing the wafer.Block 895 may comprise dicing the wafer in any of a variety of manners,non-limiting examples of which are presented herein. Block 895 may, forexample, share any or all characteristics with block 295 of the examplemethod 200 shown at FIG. 2 and discussed herein.

The discussion herein has generally focused on discussing processing ofa single die of the RD wafer. Such focus on a single die of the RD waferis for illustrative clarity only. It should be understood that all ofthe process steps (or blocks) discussed herein may be performed on anentire wafer. For example, each of the illustrations provided at FIGS.7A-7L and other figures herein may be replicated tens or hundreds oftimes on a single wafer. For example, until dicing, there might be noseparation between one of the illustrated device assemblies and aneighboring device assembly of the wafer.

Block 895 may, for example, comprise dicing (e.g., mechanicalpunch-cutting, mechanical saw-cutting, later cutting, soft beam cutting,plasma cutting, etc.) the individual packages from the wafer. The endresult of such dicing may, for example, be the package shown in FIG. 7 .For example, the dicing may form side surfaces of the package comprisingcoplanar side surfaces of a plurality of components of the package. Forexample, any or all of side surfaces of the mold material 730, the RDstructure 710 dielectric layers, the RDL dielectric layer 771, underfill728, etc., may be coplanar.

In general, block 895 may comprise dicing the wafer. Accordingly, thescope of this disclosure should not be limited by characteristics of anyparticular manner of dicing a wafer.

The example method 800 may, at block 896, comprise preparing asubstrate, or wafer or panel thereof, for attachment of the assembly700I thereto. Block 896 may comprise preparing a substrate in any of avariety of manners, non-limiting examples of which are presented herein.Block 896 may, for example, share any or all aspects with blocks 205 and210 of the example method 200 shown in FIG. 2 and discussed herein.

The substrate may, for example, comprise characteristics of any of avariety of substrates. For example, the substrate may comprise a packagesubstrate, motherboard substrate, laminate substrate, molded substrate,semiconductor substrate, glass substrate, etc.). Block 896 may, forexample, comprise preparing front side and/or backside surfaces of thesubstrate for electrical and/or mechanical attachment. Block 896 may,for example, leave a panel of substrates in a panel form at this stageand excise individual packages later, or may excise individualsubstrates from a panel at this stage.

Block 896 may also comprise receiving the substrate from an adjacent orupstream manufacturing station at a manufacturing facility, from anothergeographical location, etc. The substrate may, for example, be receivedalready prepared or additional preparation steps may be performed.

FIG. 7J provides an example illustration of various aspects of block896. For example, the assembly 700J includes an example substrate 793that was prepared for attachment.

In general, block 896 may comprise preparing a substrate, or wafer orpanel thereof, for attachment of the assembly 700I thereto. Accordingly,the scope of various aspects of this disclosure should not be limited bycharacteristics of particular substrates or by characteristics of anyparticular manner of preparing a substrate.

The example method 800 may, at block 897, comprise attaching an assemblyto the substrate. Block 897 may comprise attaching an assembly (e.g., anassembly 700I as exemplified at FIG. 7I or other assembly) in any of avariety of manners, non-limiting examples of which are presented herein.Block 897 may, for example, share any or all characteristics with block220 of the example method 200 shown in FIG. 2 and discussed herein.

The assembly may comprise characteristics of any of a variety ofassemblies, non-limiting examples of which are presented herein, forexample in all of the figures and/or related discussions herein. Block897 may comprise attaching the assembly in any of a variety of manners.For example, block 897 may comprise attaching the assembly to thesubstrate utilizing mass reflow, thermocompression bonding (TCB),conductive epoxy, etc.

FIG. 7J provides an example illustration of various aspects of block897, for example assembly attachment aspects. For example, the assembly700I shown at FIG. 7I is attached to the substrate 793.

Though not shown in FIG. 7J, in various example implementations (e.g.,as shown in FIGS. 7K and 7L), interconnection structures, for examplethrough mold interconnection structures, may be formed on the substrate793. In such example implementations, block 897 may share any or allcharacteristics with block 215 of the example method 200 shown in FIG. 2and discussed herein, albeit with regard to forming the interconnectionstructures on the substrate 793. Note that such interconnectionstructures may be performed before or after the assembly attachment, ormay also be performed before or after the underfilling at block 898.

In general, block 897 comprises attaching an assembly to the substrate.Accordingly, the scope of this disclosure should not be limited bycharacteristics of any particular assembly, substrate, or manner ofattaching an assembly to a substrate.

The example method 800 may, at block 898, comprise underfilling theassembly on the substrate. Block 898 may comprise any of a variety ofmanners of underfilling, non-limiting examples of which are presentedherein. Block 898 may, for example, share any or all characteristicswith block 825 and/or with block 225 of the example method 200 shown inFIG. 2 and discussed herein.

For example, after assembly attachment at block 897, block 898 maycomprise underfilling the attached assembly utilizing a capillaryunderfill. For example, the underfill may comprise a reinforced polymermaterial viscous enough to flow between the assembly and the substratein a capillary action.

Also for example, block 897 may comprise underfilling the semiconductordie utilizing a non-conductive paste (NCP) and/or a non-conductive film(NCF) or tape while the assembly is being attached at block 897 (e.g.,utilizing a thermocompression bonding process). For example, suchunderfill materials may be deposited (e.g., printed, sprayed, etc.)prior to attaching the assembly.

As with all of the blocks illustrated in the example method 800, block898 may be performed at any location in the method 8900 flow so long asthe space between the assembly and the substrate is accessible.

The underfilling may also occur at a different block of the examplemethod 800. For example, the underfilling may be performed as part ofthe substrate molding block 899 (e.g., utilizing a molded underfill).

FIG. 7K provides an example illustration of various aspects of block898, for example the underfilling aspects. The underfill 794 ispositioned between the assembly 700I and the substrate 793.

Though the underfill 794 is generally illustrated to be flat, theunderfill may rise up and form fillets on the sides of the assembly 700and/or other components. In an example scenario, at least a fourth or atleast a half of the assembly 700 side surfaces may be covered by theunderfill material. In another example scenario, one or more or all ofthe entire side surfaces of the assembly 700I may be covered by theunderfill material. Also for example, a substantial portion of the spacedirectly between the assembly 700I and other components and/or betweenother components (shown in various figures) may be filled with theunderfill material 794. For example, at least half of the space or allof the space between the assembly 700I and a laterally adjacentcomponent may be filled with the underfill material.

As shown in FIG. 7J, the assembly 700J may comprise a first underfill728 between the die 725, 726 and the RD structure 710, and a secondunderfill 794 between the RD structure 710 and the substrate 793. Suchunderfills 728, 794 may, for example, be different. For example, in anexample scenario in which the distance between the die 725, 726 and theRD structure 710 is less than the distance between the RD structure 710and the substrate 793, the first underfill 728 may generally comprise asmaller filler size (or have higher viscosity) than the second underfill794. In other words, the second underfill 794 may be less expensive thanthe first underfill 728.

Also, the respective underfilling processes performed at block 898 and825 may be different. For example, block 825 may comprise utilize acapillary underfill procedure, while block 898 may comprise utilizing anon-conductive paste (NCP) underfill procedure.

In another example, blocks 825 and 898 may comprise being performedsimultaneously in a same underfilling process, for example after block897. Additionally, as discussed herein, a molded underfill may also beutilized. In such an example scenario, block 899 may comprise performingthe underfilling of either or both of blocks 825 and/or 898 during thesubstrate molding process. For example, block 825 may compriseperforming a capillary underfill, while block 898 is performed at block899 as a mold underfill process.

In general, block 898 may comprise underfilling the assembly and/orother components attached to the substrate at block 897. Accordingly,the scope of this disclosure should not be limited by characteristics ofany particular type of underfill nor of any particular manner ofperforming underfilling.

The example method 800 may, at block 899, comprise molding thesubstrate. Block 899 may comprise performing such molding in any of avariety of manners, non-limiting examples of which are presented herein.Block 899 may, for example, share any or all characteristics with block830 and/or block 230 of the example method 200 shown in FIG. 2 anddiscussed herein.

For example, block 899 may comprise molding over the top surface of thesubstrate, over the assembly attached at block 897, over TMVinterconnection structures if formed on the substrate (e.g., conductiveballs, ellipsoids, columns or pillars (e.g., plated pillars, wires orwirebond wires, etc.), etc.).

Block 899 may, for example, comprise utilizing transfer molding,compression molding, etc. Block 899 may, for example, comprise utilizinga panel-molding process in which a plurality of the substrates areconnected in a panel and molded together, or block 899 may comprisemolding the substrate individually. In a panel-molding scenario, afterthe panel molding, block 899 may comprise performing an excising processin which individual substrates are separated from the substrate panel.

The molding material may, for example, comprise any of a variety ofcharacteristics. For example, the molding material (e.g., epoxy moldcompound (EMC), epoxy resin molding compound, etc.) may comprise arelatively high modulus, for example to provide package support in asubsequent process. Also for example, the molding material may comprisea relatively low modulus, to provide package flexibility in a subsequentprocess.

Block 899 may, for example, comprise utilizing a mold material that isdifferent from the mold material utilized at block 830. For example,block 899 may utilize a mold material with a lower modulus than the moldmaterial utilized at block 830. In such a scenario, the central areas ofthe assembly may be relatively stiffer than the perimeter areas of theassembly, providing for the absorption of various forces in more robustareas of the assembly.

In an example scenario in which the mold material 735 of the assembly700K and the mold material 730 of the assembly 700I are different and/orformed at different stages and/or formed utilizing different types ofprocesses, block 899 (or another block) may comprise preparing the moldmaterial 730 for adhesion to the mold material 735. For example, themold material 730 may be physically or chemically etched. The moldmaterial 730 may, for example, be plasma etched. Also for example,grooves, indentations, protrusions, or other physical features may beformed on the mold material 730. Further for example, an adhesive agentmay be placed on the mold material 730.

Block 899 may, for example, utilize a different type of molding processthan utilized at block 830. In an example scenario, block 830 mayutilize a compression molding process, while block 899 utilizes atransfer molding process. In such an example scenario, block 830 mayutilize a mold material that is specifically adapted to compressionmolding, and block 899 may utilize a mold material that is specificallyadapted to transfer molding. Such molding materials may, for example,have distinctly different material characteristics (e.g., flowcharacteristics, cure characteristics, hardness characteristics,particle size characteristics, chemical compound characteristics, etc.).

As explained herein, for example with regard to block 898, the moldingprocess of block 899 may provide underfill between the assembly 700I andthe substrate 793 and/or may provide underfill between the die 725, 726and the RD structure 710. In such an example, there may be uniformity ofmaterial between the molded underfill material and the mold materialencapsulating the substrate 793 and assembly 700I and/or the moldmaterial encapsulating the RD structure 710 and semiconductor die 725,726.

FIG. 7K provides an example illustration of various aspects of block899, for example the molding aspects. For example, the molded assembly700K is shown with the mold material 735 covering the interconnectionstructures 795 and the assembly 700. Though the mold material 735, whichmay also be referred to herein as encapsulant, is shown leaving the topof the assembly 700I exposed, this need not be the case. For example,block 899 may completely cover the assembly 700I and need not befollowed by a thinning (or grinding) operation to expose the top of theassembly 700I.

The mold material 735 may generally, for example, directly contact andcover portions of the assembly 700I that are not covered by theunderfill 794. For example in a scenario in which at least a firstportion of the sides of the assembly 700I is covered by underfill 794,the mold material 735 may directly contact and cover a second portion ofthe sides of the assembly 700I. Also, the mold material 735 may extendlaterally to the edge of the substrate 793 and thus comprise a sidesurface that is coplanar with the substrate 793. Such an assembly may,for example, be formed with panel-molding, followed by singulation ofseparate packages from the panel.

In general, block 899 may comprise molding the substrate. Accordingly,the scope of this disclosure should not be limited by characteristics ofany particular molding material, structure and/or technique.

The example method 800 may, at block 886, comprise forminginterconnection structures on the substrate, for example on the side ofthe substrate opposite the side to which the assembly is attached atblock 897. The interconnection structures may comprise characteristicsof any of variety of types of interconnection structures, for examplestructures that may be utilized to connect a semiconductor package toanother package or to a motherboard. For example, the interconnectionstructures may comprise conductive balls (e.g., solder balls) or bumps,conductive posts, etc.

FIG. 7K provides an example illustration of various aspects of block886, for example the interconnection-forming aspects. For example, theinterconnection structures 792 are illustrated attached to lands 791 ofthe substrate 793.

In general, block 886 may comprise forming interconnection structures onthe substrate. Accordingly, the scope of this disclosure should not belimited by characteristics of particular interconnection structures orby any particular manner of forming such structures.

As discussed herein, the underfill 728 may cover at least a portion ofthe sides of the die 725, 726, and/or the underfill 794 may cover atleast a portion of the sides of the assembly 700. FIG. 7L provides anillustrative example of such coverage. For example, the assembly 700I isshown with the underfill 728 contacting a portion of the sides of thedie 725, 726. As discussed herein, during a dicing process, theunderfill 728 may also be diced, resulting in an assembly 700I thatcomprises a planar side surface that includes a side surface of the RDstructure 710, a side surface of the mold material 730 and a sidesurface of the underfill 728.

The assembly 700L, which may also be referred to as a package, is shownwith the underfill 794 contacting a portion of the sides of the assembly700I (e.g., sides of the RD structure 710, sides of the underfill 728,and sides of the mold material 730. Note that as discussed herein, theunderfill 794 may, in various example implementations, comprise moldedunderfill that is the same material as the mold material 735. The moldmaterial 735 is shown encapsulating the substrate 793, theinterconnection structures 795, the underfill 794, and the assembly 700.Although in the example illustration, the tops of the assembly 700I andthe interconnection structures 795 are exposed from the mold material735, this need not be the case.

FIGS. 7 and 8 presented various example method aspects and variationsthereof. Other example method aspects will now be presented withreference to additional figures.

As discussed herein in the discussion of FIGS. 7 and 8 , block 835 maycomprise grinding (or otherwise thinning) the mold material 730 toexpose one or more of the die 725, 726. An example is provided at FIG.7D.

As also discussed, the mold grinding (or thinning) at block 835 need notbe performed or may be performed to an extent that still leaves the topsof the die 725, 726 covered with mold material 730. An example isprovided at FIG. 9 , in which the mold material 735 covers the tops ofthe die 725, 726 of the assembly 700I.

As also discussed herein, for example with regard to block 897 and FIGS.7K and 7L, in various example implementations, interconnectionstructures may be formed on the substrate. An example is provided atFIG. 9 . For example, though the tops of the die interconnectionstructures 795 are initially covered by the mold material 735, vias 940are ablated in the mold material 735 to reveal the interconnectionstructures 795.

Also, as discussed herein in the discussion of FIGS. 7 and 8 , invarious example implementations, TMV interconnection structures need notbe formed on the substrate. An example is provided at FIG. 10A. As shownin FIG. 10A, as opposed to FIG. 7K, there are no TMV interconnectionstructures 795 formed. Also as shown in FIG. 10A, as opposed to blockFIG. 1K, the mold material 735 does not cover interconnectionstructures.

Also for example, as explained herein, the mold grinding (or thinning)at block 899 may be skipped or performed to an extent that leaves thetops of the assembly 700I and/or at least one of the die 725, 726covered with mold material 735. FIG. 10A provides an exampleillustration of such processing. Generally, the FIG. 10A assembly 1000Ais similar to the FIG. 7K assembly 700K, less the interconnectionstructures 795 and with mold material 735 covering the assembly 700I.

Additionally, as explained herein, the mold grinding (or thinning) atblock 899 may be performed to an extent that exposes the assembly 700Iand/or one or more of the tops of the die 725, 726 thereof from the moldmaterial 735 (and/or mold material 730). FIG. 10B provides an exampleillustration of such processing. Generally, the FIG. 10B assembly 1000Bis similar to the FIG. 7K assembly 700K, less the interconnectionstructures 795.

In another example, as explained herein in the discussion of block 897,the TMV interconnections may comprise any of a variety of structures,for example a conductive pillar (e.g., plated post or pillar, verticalwire, etc.). FIG. 11A provides an example illustration of conductivepillars 1121 attached to the substrate 793. The conductive pillars 1121may, for example, be plated on the substrate 793. The conductive pillars1121 may also, for example, comprise wires (e.g., wire-bond wires)attached (e.g., wire-bond attached, soldered, etc.) to the substrate 793and extending vertically. The conductive pillars 1121 may, for example,extend from the substrate 793 to a height greater than a height of thedie 725, 726, equal to the height of one or more of the die 725, 726,less than a height of the die 725, 726, etc. Note that any number ofrows of the pillars 1121 may be formed. Generally, the FIG. 11A assembly1100A is similar to the FIG. 7K assembly 700K (less the mold compound735) with conductive pillars 1121 as interconnection structures insteadof elongated conductive balls 795.

Continuing the example, FIG. 11B illustrates the substrate 793,conductive pillars 1121, assembly 700I (e.g., semiconductor die 725,726), and underfill 794 covered with mold material 735. The molding may,for example, be performed in accordance with block 899 of the examplemethod 800. Generally, the FIG. 11B assembly 1100B is similar to theFIG. 7K assembly 700K with conductive pillars 1121 as interconnectionstructures instead of elongated conductive balls 795, and with moldmaterial 735 that has not been thinned or has not been thinned enough toexpose the assembly 700I.

Still continuing the example, FIG. 11C illustrates the mold material 735having been thinned (e.g., ground) to a desired thickness. The thinningmay, for example, be performed in accordance with block 899 of theexample method 800. Note, for example, that the conductive pillars 1121and/or the assembly 700I (e.g., including mold material 730 and/orsemiconductor die 725, 726 may also be thinned. For example, thethinning of the mold material 735 may expose the top ends of theconductive pillars 1121. If instead, however, the thinning of the moldmaterial 735 does not expose the top ends of the conductive pillars1121, a mold ablating operation may be performed. Note that although theassembly 1100C is shown with the tops of the semiconductor die 725, 726of the assembly 700I exposed, the tops need not be exposed.

Generally, the FIG. 11C assembly 1100C is similar to the FIG. 7Kassembly 700K with conductive pillars 1121 as interconnection structuresinstead of elongated conductive balls 795.

Continuing the example, the assembly 1100C shown in FIG. 11C may befurther processed by forming a redistribution layer (RDL) 1132 over themold material 735 and the assembly 700 (e.g., including the moldmaterial 730 and/or semiconductor die 725, 726 thereof). FIG. 11D showsan example of such processing. The redistribution layer 1132 may also bereferred to herein as the backside redistribution (RDL) layer 1132.Though such backside RDL forming is not explicitly shown in one of theblocks of the example method 800, such operation may be performed in anyof the blocks, for example after the block 899 mold grinding operation(if performed).

As shown in FIG. 11D, a first backside dielectric layer 1133 may beformed and patterned on the mold material 735 and the assembly 700I(e.g., including the mold material 730 and/or semiconductor die 725, 726thereof). The first backside dielectric layer 1133 may, for example, beformed and patterned in a same or similar manner to the RDL dielectriclayer 771 formed at block 855, albeit on a different surface. Forexample, the first backside dielectric layer 1133 may be formed on themold material 735 and/or on the assembly 700I (e.g., including the moldmaterial 730 and/or semiconductor die 725, 726 thereof), for exampledirectly on exposed backside surfaces of the die 725, 726, on moldmaterial 730 and/or 735 covering the backside surfaces of the die 725,726, etc., and vias 1134 may be formed (e.g., by etching, ablating,etc.) in the first backside dielectric layer 1133 to expose at least thetops of the conductive pillars 1121.

Backside traces 1135 may be formed on the first backside dielectriclayer 1133 and in the vias 1134 of the first backside dielectric layer1133. The backside traces 1135 may thus be electrically connected to theconductive pillars 1121. The backside traces 1135 may, for example, beformed in a same or similar manner to the RDL traces 782 formed at block865. At least some, if not all, of the backside traces 1135 may, forexample, extend from the conductive pillars 1121 to locations directlyabove the assembly 700I (e.g., including the mold material 730 and/orsemiconductor die 725, 726 thereof). At least some of the backsidetraces 1135 may also, for example, extend from the conductive pillars1121 to locations that are not directly above the assembly 700I (e.g.,including the mold material 730 and/or semiconductor die 725, 726thereof).

A second backside dielectric layer 1136 may be formed and patterned onthe first backside dielectric layer 1133 and backside traces 1135. Thesecond backside dielectric layer 1136 may, for example, be formed andpatterned in a same or similar manner to the RDL dielectric layer 771formed at block 855, albeit on a different surface. For example, thesecond backside dielectric layer 1136 may be formed over the firstbackside dielectric layer 1133 and over the backside traces 1135, andvias 1137 may be formed (e.g., by etching, ablating, etc.) in the secondbackside dielectric layer 1136 to expose contact areas of the backsidetraces 1135.

Backside interconnection pads 1138 (e.g., ball contact pads, lands,terminals, etc.) may be formed on the second backside dielectric layer1136 and/or in the vias 1137 of the second backside dielectric layer1136. The backside interconnection pads 1138 may thus be electricallyconnected to the backside traces 1135. The backside interconnection pads1138 may, for example, be formed in a same or similar manner to the RDLtraces formed at block 865. The backside interconnection pads 1138 may,for example, be formed by forming metal contact pads and/or formingunder bump metallization (e.g., to enhance subsequent attachment to thebackside traces 1135 by other interconnection structures).

Though the backside RDL layer 1132 is shown with two backside dielectriclayers 1133, 1136 and one layer of backside traces 1135, it should beunderstood that any number of dielectric and/or trace layers may beformed.

Though not shown in FIG. 11D, interconnection structures may be formedon the substrate 793, for example on a side of the substrate 793opposite the assembly 700I and mold material 735, as discussed hereinfor example with regard to block 886 and FIG. 7K.

In another example implementation, a substrate (e.g., a laminatesubstrate, package substrate, etc.) may be attached above the assembly700I (e.g., including the semiconductor die 725, 726, and mold material730) and the mold material 735, for example instead of or in addition tothe backside RDL discussed herein with regard to FIGS. 11A-11D.

For example, as illustrated in FIG. 12A, the interconnection structures795 may be formed at a height that will extend to at least the height ofthe assembly 700. Note that this height is not necessarily present, forexample in a scenario in which the backside substrate has its owninterconnection structures or in which additional interconnectionstructures are utilized between the interconnection structures 795 andthe backside substrate. The interconnection structures 795 may, forexample, be attached in a same or similar manner as that discussedherein with regard to block 897 and FIG. 7K.

Continuing the example, as illustrated in FIG. 12A, the assembly 1200Amay be molded with a mold material 735 and the mold material 735 may bethinned if necessary. Such molding and/or thinning may, for example, beperformed in a same or similar manner to that discussed herein withregard to block 899, and FIG. 7K.

As shown in FIG. 12B, a backside substrate 1232 may be attached. Forexample, the backside substrate 1232 may be electrically connected tothe interconnection structures 795 and/or mechanically attached to themold material 735 and/or the assembly 700I (e.g., the mold material 730and/or semiconductor die 725, 726). The backside substrate 1232 may, forexample, be attached in panel form and/or single package form, and mayfor example be attached before or after singulation.

As discussed herein, after the assembly 700I is attached to thesubstrate 793, the substrate 793 and/or assembly 700I may be coveredwith a mold material. Alternatively, or in addition, the substrate 793and/or assembly 700I may be covered with a lid or stiffener. FIG. 13provides an illustrative example. FIG. 13 generally shows the assembly700J of FIG. 7J, with the addition of a lid 1310 (or stiffener).

The lid 1310 may, for example, comprise metal and provideelectromagnetic shielding and/or heat dissipation. For example, the lid1310 may be electrically coupled to a ground trace on the substrate 793to provide shielding. The lid 1310 may, for example, be coupled to thesubstrate 793 with solder and/or conductive epoxy. Though not shown,thermal interface material may be formed in a gap 1315 between theassembly 700I and the lid 1310.

Though most of the examples shown and discussed herein have generallyonly shown the assembly 700I attached to the substrate 793, othercomponents (e.g., active and/or passive components) may also be attachedto the substrate 793. For example, as shown in FIG. 14 , a semiconductordie 1427 may be attached to the substrate 793 (e.g., flip-chip bonded,wire bonded, etc.). The semiconductor die 1427 is attached to thesubstrate 793 in a manner that is laterally adjacent to the assembly700I. After such attachment, any of the packaging structures discussedherein (e.g., interconnection structures, moldings, lids, etc.) may thenbe formed.

In another example implementation, other components may be coupled tothe top side of the assembly 700I, in a vertical stacking assembly. FIG.15 shows an example of one such assembly 1500C. A third die 1527 and afourth die 1528 (e.g., the inactive sides thereof) may be attached tothe top of the assembly 700I. Such attachment may, for example, beperformed using adhesive. Bond pads on the active sides of the third die1527 and the fourth die 1528 may then be wire-bonded to the substrate793. Note that in a scenario in which an RDL and/or substrate isattached over the assembly 700, the third die 1527 and/or fourth die1528 may be flip-chip bonded to such RDL and/or substrate. After suchattachment, any of the packaging structures discussed herein (e.g.,interconnection structures, moldings, lids, etc.) may then be formed.

In yet another example implementation, another component may be coupledto the bottom side of the substrate. FIG. 16 shows an example of onesuch assembly. A third die 1699 is attached to the bottom side of thesubstrate 793, for example in a gap between interconnection structureson the bottom side of the substrate 793. After such attachment, any ofthe packaging structures discussed herein (e.g., interconnectionstructures, moldings, lids, etc.) may then be formed.

The example methods and assemblies shown in FIGS. 8-16 and discussedherein are merely non-limiting examples presented to illustrate variousaspects of this disclosure. Such methods and assemblies may also shareany or all characteristics with the methods and assemblies shown anddiscussed in the following co-pending United States patent applications:U.S. patent application Ser. No. 13/753,120, filed Jan. 29, 2013, andtitled “SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTORDEVICE”; U.S. patent application Ser. No. 13/863,457, filed on Apr. 16,2013, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHODTHEREOF”; U.S. patent application Ser. No. 14/083,779, filed on Nov. 19,2013, and titled “SEMICONDUCTOR DEVICE WITH THROUGH-SILICON VIA-LESSDEEP WELLS”; U.S. patent application Ser. No. 14/218,265, filed Mar. 18,2014, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHODTHEREOF”; U.S. patent application Ser. No. 14/313,724, filed Jun. 24,2014, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHODTHEREOF”; U.S. patent application Ser. No. 14/444,450, Jul. 28, 2014,and titled “SEMICONDUCTOR DEVICE WITH THIN REDISTRIBUTION LAYERS”; U.S.patent application Ser. No. 14/524,443, filed Oct. 27, 2014, and titled“SEMICONDUCTOR DEVICE WITH REDUCED THICKNESS”; U.S. patent applicationSer. No. 14/532,532, filed Nov. 4, 2014, and titled “INTERPOSER,MANUFACTURING METHOD THEREOF, SEMICONDUCTOR PACKAGE USING THE SAME, ANDMETHOD FOR FABRICATING THE SEMICONDUCTOR PACKAGE”; U.S. patentapplication Ser. No. 14/546,484, filed Nov. 18, 2014, and titled“SEMICONDUCTOR DEVICE WITH REDUCED WARPAGE”; and U.S. patent applicationSer. No. 14/671,095, filed Mar. 27, 2015, and titled “SEMICONDUCTORDEVICE AND MANUFACTURING METHOD THEREOF;” the contents of each of whichare hereby incorporated herein by reference in their entirety

The discussion herein included numerous illustrative figures that showedvarious portions of a semiconductor package assembly. For illustrativeclarity, such figures did not show all aspects of each example assembly.Any of the example assemblies presented herein may share any or allcharacteristics with any or all other assemblies presented herein. Forexample and without limitation, any of the example assemblies shown anddiscussed with regard to FIGS. 1-7 , or portions thereof, may beincorporated into any of the example assemblies discussed with regard toFIGS. 8-16 . Conversely, any of the assemblies shown and discussed withregard to FIGS. 8-16 may incorporated into the assemblies shown anddiscussed with regard to FIGS. 1-7 .

In summary, various aspects of this disclosure provide a semiconductordevice or package structure and a method for making thereof. While theforegoing has been described with reference to certain aspects andexamples, it will be understood by those skilled in the art that variouschanges may be made and equivalents may be substituted without departingfrom the scope of the disclosure. In addition, many modifications may bemade to adapt a particular situation or material to the teachings of thedisclosure without departing from its scope. Therefore, it is intendedthat the disclosure not be limited to the particular example(s)disclosed, but that the disclosure will include all examples fallingwithin the scope of the appended claims.

What is claimed is:
 1. A semiconductor device comprising: a front sideredistribution structure (“FSRDS”) comprising: a top FSRDS side; abottom FSRDS side; a lateral FSRDS side between the top FSRDS side andthe bottom FSRDS side; a first FSRDS dielectric layer; and a first FSRDSconductive layer comprising a first FSRDS conductive trace; asemiconductor die comprising a front die side and a back die side, thefront die side facing toward and coupled to the top FSRDS side, thefront die side comprising a conductive pad that is electrically coupledto the first FSRDS conductive layer; a stacked component interconnectionstructure (“SCIS”) comprising a top SCIS side and a bottom SCIS side,the bottom SCIS side coupled to the top FSRDS side and electricallycoupled to the first FSRDS conductive layer, the top SCIS side extendingvertically at least as high as the back die side; an encapsulatingmaterial on the top FSRDS side and laterally surrounding thesemiconductor die, the encapsulating material comprising: a topencapsulating material side; a bottom encapsulating material side facingthe front side redistribution structure; and a lateral encapsulatingmaterial side between the top encapsulating material side and the bottomencapsulating material side; a back side redistribution structure(“BSRDS”) comprising: a top BSRDS side; a bottom BSRDS side coupled tothe top SCIS side; a first BSRDS dielectric layer on the back die sideand on the top encapsulating material side; and a first BSRDS conductivelayer comprising a first BSRDS conductive trace that is electricallycoupled to the stacked component interconnection structure; and anunderfill material between and in contact with the front die side andthe top FSRDS side; wherein the front side redistribution structurecomprises a build-up redistribution structure, and the back sideredistribution structure comprises a laminate substrate.
 2. Thesemiconductor device of claim 1, wherein the stacked componentinterconnection structure comprises a copper-core solder structure. 3.The semiconductor device of claim 1, wherein the stacked componentinterconnection structure comprises an elongated conductive ball.
 4. Thesemiconductor device of claim 1, wherein: the stacked componentinterconnection structure comprises a core of a first metal surroundedby a second metal; and the encapsulating material laterally surrounds anentirety of the core.
 5. The semiconductor device of claim 1, whereinthe back die side is exposed from the encapsulating material.
 6. Thesemiconductor device of claim 1, wherein the bottom BSRDS side ismechanically attached to the back die side.
 7. The semiconductor deviceof claim 1, wherein the bottom BSRDS side is mechanically attached tothe encapsulating material.
 8. The semiconductor device of claim 1,wherein: the back side redistribution structure comprises a lateralBSRDS side between the top BSRDS side and the a bottom BSRDS side; andthe lateral FSRDS side, the lateral encapsulating material side, and thelateral BSRDS side are coplanar.
 9. The semiconductor device of claim 1,wherein: the semiconductor die comprises a lateral die side between thefront die side and the back die side; and the underfill material is incontact with the lateral die side.
 10. A semiconductor devicecomprising: a first side redistribution structure (“FSRDS”) comprising:a first FSRDS side; a second FSRDS side opposite the first FSRDS side; alateral FSRDS side between the first FSRDS side and the second FSRDSside; a first FSRDS dielectric layer; and a first FSRDS conductive layercomprising a first FSRDS conductive trace; a semiconductor diecomprising a first die side, a second die side opposite the first dieside, and a lateral die side between the first die side and the seconddie side, the second die side facing toward and coupled to the firstFSRDS side; a stacked component interconnection structure (“SCIS”)comprising a first SCIS side and a second SCIS side opposite the firstSCIS side, the second SCIS side coupled to the first FSRDS side andelectrically coupled to the first FSRDS conductive layer, the stackedcomponent interconnect structure vertically spanning an entirety of thesemiconductor die; an encapsulating material on the first FSRDS side andlaterally surrounding the semiconductor die, the encapsulating materialcomprising: a first encapsulating material side; a second encapsulatingmaterial side opposite the first encapsulating material side and facingthe first side redistribution structure; and a lateral encapsulatingmaterial side between the first encapsulating material side and thesecond encapsulating material side; a second side redistributionstructure (“SSRDS”) comprising: a first SSRDS side; a second SSRDS sideopposite the first SSRDS side and coupled to the first SCIS side; alateral SSRDS side between the first SSRDS side and the second SSRDSside; a first SSRDS dielectric layer; and a first SSRDS conductive layercomprising a first SSRDS conductive trace that is electrically coupledto the stacked component interconnection structures; and an underfillmaterial directly vertically between the first die side and the firstFSRDS side; wherein the underfill material laterally extends beyond thelateral die side; and wherein: one of the first side redistributionstructure and the second side redistribution structure comprises abuild-up redistribution structure; and another of the first sideredistribution structure and the second side redistribution structurecomprises a laminate substrate.
 11. The semiconductor device of claim10, wherein the second side redistribution structure comprises alaminate substrate.
 12. The semiconductor device of claim 10, whereinthe semiconductor die comprises a die pad on the second die side. 13.The semiconductor device of claim 10, wherein the lateral FSRDS side,the lateral encapsulating material side, and the lateral SSRDS side arecoplanar.
 14. The semiconductor device of claim 10, wherein the stackedcomponent interconnection structure comprises a copper-core solderstructure.
 15. The semiconductor device of claim 10, wherein underfillmaterial contacts and covers at least a portion of the lateral die side.16. The semiconductor device of claim 10, wherein the second SSRDS sideis mechanically attached to the first die side.
 17. A method of making asemiconductor device, the method comprising: providing a first sideredistribution structure (“FSRDS”) comprising: a first FSRDS side; asecond FSRDS side opposite the first FSRDS side; a lateral FSRDS sidebetween the first FSRDS side and the second FSRDS side; a first FSRDSdielectric layer; and a first FSRDS conductive layer comprising a firstFSRDS conductive trace; providing a semiconductor die comprising a firstdie side, a second die side opposite the first die side, and a lateraldie side between the first die side and the second die side, the seconddie side facing toward and coupled to the first FSRDS side; providing astacked component interconnection structure (“SCIS”) comprising a firstSCIS side and a second SCIS side opposite the first SCIS side, thesecond SCIS side coupled to the first FSRDS side and electricallycoupled to the first FSRDS conductive layer, the stacked componentinterconnect structure vertically spanning an entirety of thesemiconductor die; providing an encapsulating material on the firstFSRDS side and laterally surrounding the semiconductor die, theencapsulating material comprising: a first encapsulating material side;a second encapsulating material side opposite the first encapsulatingmaterial side and facing the first side redistribution structure; and alateral encapsulating material side between the first encapsulatingmaterial side and the second encapsulating material side; and providinga second side redistribution structure (“SSRDS”) comprising: a firstSSRDS side; a second SSRDS side opposite the first SSRDS side andcoupled to the first SCIS side; a lateral SSRDS side between the firstSSRDS side and the second SSRDS side; a first SSRDS dielectric layer;and a first SSRDS conductive layer comprising a first SSRDS conductivetrace that is electrically coupled to the stacked componentinterconnection structure, providing an underfill material directlyvertically between the first die side and the first FSRDS side such thatthe underfill material laterally extends beyond the lateral die side;wherein: one of the first side redistribution structure and the secondside redistribution structure comprises a build-up redistributionstructure; and another of the first side redistribution structure andthe second side redistribution structure comprises a laminate substrate.18. The method of claim 17, wherein the second side redistributionstructure comprises a laminate substrate.
 19. The method of claim 17,comprising forming the lateral FSRDS side, the lateral encapsulatingmaterial side, and the lateral SSRDS side to be coplanar.
 20. The methodof claim 17, providing the underfill material directly such that theunderfill material contacts and covers at least a portion of the lateraldie side.